Decimation filter design for RSFQ ΣΔ converter

In order to develop superconducting over-sampled AD converter, based on a band pass sigma delta modulator, we study a sinc decimation filter using top-down method: Matlab simulations are performed to determine filter specifications, VHDL behavioral model of the complete architecture (sigma delta AD converter, I/Q mixer and low pass decimation filter) is realized to validate decimation filter performance and finally SFQ elementary cells are implemented using VHDL-AMS tool.