Low-overhead, digital offset compensated, SRAM sense amplifiers

Device variability in modern processes has become a major concern in SRAM design, degrading performance, yield, power, and reliability. While low-swing bitlines can reduce power consumption and increase performance, offset in the sense amplifiers due to device variability hinders the scalability of this technique. A promising method for decreasing the offset is post-silicon tuning using digitally controlled offset compensation. Thus, we have designed and implemented low-overhead, digital offset compensated, SRAM sense amplifiers using both the latch-style and StrongARM topologies. Measured results from a 4 mm
²
testchip design in a 45 nm bulk CMOS process containing 3000 sense amplifier instances per chip show that we can reduce the standard deviation of offset (sigma
_OFFSET
) by over 5x.