Throughput Analysis, Optimal Buffer Allocation, and Traffic Imbalance Study of a Generic Nonblocking Packet Switch

This paper provides a general model to study the performance of a family of space-domain packet switches, implementing both input and output queueing and varying degrees of speedup. Based on this model, the impact of the speedup factor on the switch performance is analyzed. In particular, the maximum switch throughput and the average system delay for any given degree of speedup are obtained. The results demonstrate that the switch can achieve 99% throughput with a modest speedup factor of 4.

Packet blocking probability for systems with finite buffers can also be derived from this model and the impact of buffer allocation on blocking probability is investigated. Given a fixed buffer budget, this analysis obtains an optimal placement of buffers among input and output ports to minimize the blocking probability.

The model is also extended to cover a nonhomogeneous system where traffic intensity at each input varies and destination distribution is not uniform. Using this model, the impact of traffic imbalance on the maximum switch throughput is studied. It is seen that input imbalance has a more adverse effect on throughput than output imbalance. It is also observed that, under the same input imbalance conditions, the throughput reduction is more significant for switches with higher speedup while, under the same output imbalance conditions, this trend is reversed.