Derivation of Minimal Test Sets for Monotonic Logic Circuits | IEEE Journals & Magazine | IEEE Xplore

Derivation of Minimal Test Sets for Monotonic Logic Circuits


Abstract:

It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredu...Show More

Abstract:

It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredundant two-level realization of a 2-monotonic function.
Published in: IEEE Transactions on Computers ( Volume: C-22, Issue: 7, July 1973)
Page(s): 657 - 661
Date of Publication: 29 May 2009

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