155.52 Mbits/s parallel frame synchronous scheme for SDH networks

This paper presents an entirely novel parallel processing based frame synchronous system for 155.520 Mbps high speed networks according to the CCITT recommendations G.707, G.708 and G.709. This scheme is expected to relax operating speed requirements of the circuits used in the system. The proposed methodology can be implemented using off-the-shelf low-rate integrated circuits (ICs). The performance of the devised methodology is analyzed and found to be similar to that of the traditional approaches. Finally, the proposed scheme is efficient, easy to implement at low cost without sacrificing performance.