Improvement of performance of Drain-Source-On-Insulator MOSFETs by using heavily doped-Si region between local BOX regions

Silicon On Insulator (SOI) MOSFETs have three problems due to Buried Oxide (BOX) layer: (1) suppression of thermal diffusion out of the SOI layer, (2) accumulation of excess carrier in the SOI layer, and (3) capture of carriers at trap states at the SOI/BOX interface. To reduce problems of thermal diffusion and excess carrier, Drain Source On Insulator (DSOI) MOSFETs were proposed. We simulate electrical behavior of DSOI MOSFETs and show those are not suitable for shrinking because of bulk punch through issue. And so, we proposed an advanced DSOI structure which silicon between local BOX region is heavily doped and we show subthreshold slope less than 100 [mV/dec.] when gate length is 30 [nm]. Also we show difference of thermal distribution between SOI and DSOI causes by structure.