Low-Power Race-Free Programmable Logic Arrays

Conventional programmable logic arrays (PLAs) implement both the AND and OR logic planes with dynamic NOR gates. They are fast, regular in structure and easy to program. However, they have high power dissipation and suffer from an inherent timing race that increases design effort, reduces circuit robustness in the presence of variations, and adversely impacts performance. In this paper, a PLA which implements the AND plane as a hierarchical combination of dynamic NAND gates and retains the dynamic NOR gate based OR plane is presented. The NAND-NOR PLA architecture completely eliminates the critical timing race between the logic planes and has significantly lower power dissipation than the conventional PLA. Simulated energy-delay product of an optimized design on a foundry 130 nm low standby power process shows that the proposed circuit architecture has 43% lower energy-delay product than the conventional PLA design. The fabricated circuits have been tested fully functional on silicon demonstrating a maximum operating frequency of 1.61 GHz at V
_DD
= 1.6 V.