PMChip: an ASIC dedicated to pipelined read out and trigger systems

We describe a custom VLSI circuit, which is the main component of the read out system for some of the detectors of the NA48 experiment at the CERN SPS. Such a readout system is conceived to be completely dead time free and is based on a pipelined architecture. Our ASIC contains an 8 k circular memory, where data from ADC cards are stored continuously and can be retrieved after the time needed by the global trigger to make its decisions. It also contains a 256 locations output buffer for triggered data. The whole memory control logic has been integrated inside the ASIC. The VLSI approach allows us to implement a number of very useful features which could not be possible on a discrete component system.<
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