A fault-tolerant CEQRNS processing element for linear systolic array DSP applications

The design of a Galois enhanced quadratic residue number system (GEQRNS) processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been optimized to perform multiply-accumulate type operations on complex operands. The properties of finite fields have been exploited to perform this complex multiplication in a manner which results in greatly reduced hardware complexity. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which can occur during operation. The combination of these two factors makes this an ideal candidate for array signal processing applications, where high complex arithmetic data rates are required. A prototype processing element has been fabricated in 1.5 /spl mu/m CMOS technology, which is shown to operate at 40 MHz.<
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