Transconductance-based CMOS analog multiplier

In this paper we propose a four-quadrant multiplier based on a core cell that exploits the relationship between the saturation current of an MOS transistor and the source transconductance. The advantages of the proposed topology are simplicity and feasibility of low-power and low-voltage operation. Experimental results in a 0.35 μm CMOS prototype indicate 1 mA consumption for 1MHz bandwidth, and distortion level below 1% for an input current equal to 80% of the full scale range. The multiplier area is around 10,000 μm
²
.