Design and optimisation of a high current, high frequency monolithic buck converter

The detailed design and optimisation of a high current monolithic point-of-load (POL) buck converter is presented in this paper. The approach taken is to identify the major design issues which account for power losses and represent them as a function of the power device width. Having identified these loss sources and quantified them, the optimum power device sizes are obtained for a converter with a 20 MHz switching frequency.