Ultra Low Power ASIP Design for Wireless Sensor Nodes

This work presents a methodology for designing an ultra low power application specific instruction set processor. This paper shows the different steps to develop a digital signal processing architecture for a single channel ECG application assuming a system level power dissipation constraint of 100 μW. We follow a bottleneck driven approach based on the following steps. First coarse grained clock gating is applied. Next, the static as well as the dynamic dissipation of the digital processor is reduced and possibilities for future improvements are discussed. Finally, an optimal processor is built consuming 8.40 μW when running the reference application.