Punch-through Effects in RF Bulk LDMOS Transistors

The design and electrical performances of Bulk Silicon power LDMOS transistors for base station applications are analyzed in this paper. Power LDMOS transistors have been fabricated with a 7 mask levels process technology including a LOCOS in the drift region and a polysilicon field plate. On-state resistances in the range of 6 mΩx cm
²
have been experimentally measured on 80 V transistors. Moreover, the impact of the basic geometrical and technological parameters on the voltage capability and the on-state resistance is also analyzed with special emphasis on the premature punch-through breakdown due to excessive phosphorous dose in the drift region. Technological solutions for avoiding this undesired mechanism are discussed. The evolution of the gate-to-drain capacitance versus the drift dose is also described.