Evaluation of High Throughput Turbo-Decoder Architectures

The outstanding forward error correction of Turbo-Codes made them part of many today's communications standards. For high throughput applications, efficient parallel Turbo-Decoder architectures are key. In this paper we compare two fundamentally different parallel architectural approaches in terms of performance and implementation complexity. Both architectures exploit the well known windowing scheme. The first architecture template processes several windows in parallel. Each window is executed on a serial Log-MAP decoder which produces one value per clock cycle. In contrast, the second architecture sequentially processes the individual windows on a fast monolithic pipelined MAP decoder which produces several values per clock cycle and is memory-optimized. This is to the best of our knowledge the first comparison of this totally different architectural approaches for high throughput Turbo-Decoder architectures. We apply the 3GPP conditions for performance comparisons.