Development of 130nm CMOS Monolithic Active Pixels with In-pixel Signal Processing

We developed monolithic active pixel detectors that exploit the triple well option of CMOS 130 nm technology to implement analog and digital signal processing at the pixel level. The charge collecting element is realized using the deep N-well (DNW) and partially overlaps the analog circuit. With this scheme we were able to implement a full in-pixel signal processing chain, composed of a charge preamplifier, shaper, discriminator, and latch. This approach has been validated by a first prototype (APSEL0), and we report here on the extensive measurements performed on the second prototype (APSEL1), containing various single pixel structures with analog readout and an 8 times 8 matrix of 50 times 50 mum
²
pixels with sequential digital readout. For 900 mum
²
pixels the equivalent noise charge has been measured to be 40 e
^-
, with a S/N ratio of about 30 for the
⁵⁵
Fe 5.9 keV signal. The matrix readout has been tested up to 30 MHz and the crosstalk between pixels characterized. The threshold dispersion and the noise of the pixels in the matrix have been measured through noise scans. These measurements confirm the viability of the triple well process for MAPS fabrication, and indicate the design improvements for the next prototype chip (APSEL2).