VLSI implementation of a 100 MHz pipelined ADPCM codec chip

The VLSI implementation of a pipelined adaptive differential pulse-code modulation (ADPCM) video codec is described. The architecture for the ADPCM codec had been developed previously via the relaxed look-ahead technique. The results of this technique is a bit-parallel and bit-level pipelined architecture with minimal hardware overhead. All the arithmetic units employ redundant authors for low-latency, carry-free computatron. The pipelining latches are true single-phase and edge-triggered with a very compact structure. The pipelined ADPCM chip is designed in 1.2/spl mu/ CMOS technology, with a total area of 5.6 /spl times/ 8.8 mm/sup 2/, an active area of 5.1 /spl times/ 8.2 mm/sup 2/ (136,000 transistors) and a projected speed of 100 MHz. This chip can be configured both as an encoder and a decoder. The codec has a compression ratio of a 8:3 for a 256 /spl times/ 256 image frame.<
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