On the Series-to-Parallel Transformation of Linear Sequential Circuits

In a recent paper,
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Hsiao and Sih proposed a method for transforming binary linear feedback shift registers (initially cleared) into a binary linear circuit with f input terminals and f output terminals which operates f times faster. In this manner, the availability of f channels, rather than one, can be exploited to process (and, in particular, encode and decode) data at a rate proportional to f. In this paper, a method of transformation is formulated which is applicable to arbitrary linear sequential circuits defined over an arbitrary modular field and subject to an arbitrary initial state.