Optimization of salicide processes for sub 0.1-/spl mu/m CMOS devices

In scaled CMOS devices with gate less than 0.1 /spl mu/m long, the reduced gate resistance obtained using salicide is a key issue for high-speed performance Recently, many studies have examined salicide processes for short gates. A low gate resistance with gates less than 0.1 /spl mu/m long has not been reproducibly obtained, however, because of agglomeration. We studied the disadvantages of the conventional Ti, Pt and Co salicide for 0.1-/spl mu/m CMOS devices. We developed an improved Co salicide process which fabricated devices at gates less than 0.1-/spl mu/m long with a low gate resistance and good electrical properties.<
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