Characteristics of a 'HARP' signal processor with analog memory operated with segmented silicon detectors

A 32 channel analog VLSI detector readout chip (HARP32) with an input charge preamplifier, a 64-cell current integrating analog memory in each channel and a common analog multiplexer, has been used in a test beam with segmented silicon detectors. The device was operated at the LHC clock speed of 66 MHz. The different pedestal variations seen at the output are analyzed: the input noise /spl sigma//sub n/ amounts to 2.8mV r.m.s., the pedestal non-uniformity in channel /spl sigma//sub ped/ to 1.2 mV r.m.s., the channel to channel pedestal variation /spl sigma//sub ch/ to 4.0 mV r.m.s., and an output baseline shift /spl sigma//sub obs/ of 3.5 mV r.m.s has been observed.<
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