Transistor stuck-at and delay faults detection in static and dynamic CMOS combinational gates

A technique for detection of delay faults in CMOS gates is presented. It is based on a testable design of CMOS gates and on an algorithm developed for detection of transistor stuck-at faults (stuck-open and stuck-on). This methodology can be applied to both static and dynamic CMOS gates, as shown by two examples. It is also shown that the test algorithm developed for fully CMOS logic can be easily applied to DOMINO CMOS circuits. However, in order to detect a very small set of stuck-on faults, it is necessary to monitor current drawn by the circuit.<
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