A 15 ns 16 Mb CMOS SRAM with reduced voltage amplitude data bus

A 15-ns 16-Mbit CMOS SRAM which uses a reduced voltage amplitude data bus and a hierarchical sense amplifier scheme is described. The SRAM is organized as 4 Mwords*4 bits. Fast access time and low power dissipation are obtained by a reduced-voltage-amplitude data bus connected to a latched cascaded sense amplifier and current sense amplifier. The waveforms of the address input and the data output lines at room temperature with a 3-V supply are shown. The access time is typically 15 ns, with an active current consumption of 55 mA at 3.0 V and 30 MHz.<
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