A New J-K Flip-Flop for Synchronizers

Anomalous gating of asynchronous signals in synchronizers and arbiter circuits may cause significant errors and system failures. Since the probability of logically undefined states at the output of flip-flops increases rapidly with clock rate, the errors were reduced by lower frequencies, at the price of severe time loss, until now. The paper presents a J-K flip-flop in which the duration of an oscillatory or metastable behavior is reduced by a factor of 5 to 15. In this flip-flop the switching of two gates is accelerated by tunnel diodes.