Fail-Safe Asynchronous Sequential Machines

Fail-safe circuits are designed to assume a 1 (1-fail-safe) or a 0 (0-fail-safe) output state upon failure. This correspondence extends fault detection techniques previously presented [1] to include the design of fail-safe asynchronous sequential circuits. Faults causing failures in the internal state logic and the output state logic circuitry are treated. These failures are assumed to be symmetric and the resulting circuit realizations require less hardware than realizations derived from previously presented techniques.