DPTL 4-b carry lookahead adder

Implementation of a 4-b carry lookahead adder using D-MESFETs, in 1- mu m non-self-aligned gate GaAs technology, is presented. A novel technique to improve the circuit performance using differential pass transistor logic (DPTL) is presented. Circuit structures are presented and are compared with buffered FET logic (BFL). Experimental results are provided to verify the functionality and performance of the DPTL adder. The adder occupies an area of 0.890*0.652 mm/sup 2/ (excluding the output pads) and can add up to 1 Gwords/s dissipating 242 mW of power (excluding the output drivers).<
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