Design of a Reusable IP Core; Timing Generator for Synchronous Digital Hierarchy Systems

The availability of reusable IP-cores, increasing time to market and design productivity gap, and enabling deep sub-micron technologies have led to core-based system-on-chip (SoC) design as a new paradigm in electronic system design especially in more applicable embedded systems. For this purpose, we have designed a well-verified and synthesizable IP named: "timing generator for synchronous transport module (STM-I) frame" for synchronous digital hierarchy systems base on ITU-T G707 and virtual socket interface alliance (VSIA) standards. The top level of this IP has been designed and verified in the HDS environment of cadence tools and it has been synthesized by design compiler, synopsis synthesis tool