Development of a CMOS time memory cell VLSI and a CAMAC module with 0.5 ns resolution

A CMOS time-to-digital converter chip, the time memory cell (TMC), for a high-rate wire chamber application has been developed. The chip had a timing resolution of 0.52 ns, dissipated only 7 mW/channel, and contained 4 channels in a chip. Each channel had 1024 memory locations which acted as a buffer 1 mu s deep. The chip was fabricated in a 0.8- mu m CMOS process and had dimensions of 5.0 mm by 5.6 mm. Using the TMC chip, a CAMAC module with 32 input channels was developed. This module was designed to operate in both common start and common stop modes. The module circuit and test results are described.<
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