A low-voltage CMOS 5-bit 600 MHz 30 mW SAR ADC for UWB wireless receivers

In this work, we propose a time-interleaved successive approximation register ADC (SAR) that provides the high speed conversion needed in UWB application with the minimum power consumption. The power consumption can be easily scaled down based on the demand on speed and resolution where the number of parallel SARs and the number of iterations in each SAR can be chosen according to speed and resolution requirements. Our proposed SAR ADC works with a 3 V supply voltage. A single 5-bit SAR ADC requires two clock cycles for sampling and holding and five clock cycles for data conversion. To further increase the throughput, we employ a time-interleaved architecture with ten SAR ADCs in parallel. The entire ADC is designed in AMI05 CMOS technology. In this paper, design procedures and techniques are discussed in detail.