An efficient modelling technique for computing the parasitic capacitances in VLSI circuits

An efficient method is presented to model the parasitic capacitance of VLSI interconnections. The model approximates the charge density on the conductors as a continuous function on a web of edges. Each base function in the approximation has the form of a spider of edges. The authors show that the model: (1) has very low complexity as compared to previously presented models; and (2) achieves a high degree of precision within the range of validity of the stratified medium.<
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