Inverter-based switched current circuit for very low-voltage and low-power applications

A new sample-and-hold (S/H) circuit for low-voltage and low-power CMOS analog design is proposed. The circuit is based on the conventional CMOS inverter operating as a transconductor. The proposed circuit does not require linear capacitors and employs switches that operate at fixed channel voltage. Owing to the use of inverters, the proposed structure presents class-AB operation. A S/H circuit has been designed in a standard 0.35-/spl mu/m CMOS technology at 0.6 V supply. The S/H cell operating at a clock frequency of 10 kHz consumes 30 nW and presents a dynamic range of approximately 60 dB.