A functional verification method for pipelined DSP

As the complexity and quality expectation of pipelined DSPs increases, while the time-to-market decreases, functional verification has become a more difficult process and has emerged as the bottleneck of the development cycle. In order to improve the efficiency and the effectiveness of functional verification, a novel verification for pipelined DSP is presented, which includes an automatic high-coverage self-checking model and a pipeline-based model. The former model is based on a heuristic algorithm to verify the total instructions execution of the pipelined DSP, especially the arithmetic function units, and successfully achieves a high statement hit rate close to 100% and high reliability, but requires a little manual intervention. In contrast, the later model validates the complex pipeline mechanism of the DSP completely and gets 89% statement hit rate and 93% branch hit rate, which is 2.16/spl sim/6.85 times more than that of application programs. With those two models, sufficient test programs are generated and convenient ways to confirm the execution results from the pipelined DSP are provided as well.