Device sizing for minimum energy operation in subthreshold circuits

Digital circuits operating in the subthreshold region provide the minimum energy solution for applications with strict energy constraints. This paper examines the effect of sizing on energy for subthreshold circuits. We show that minimum sized devices are theoretically optimal for reducing energy. A fabricated 0.18 /spl mu/m test chip is used to compare normal sizing and sizing for minimum V/sub DD/. Measurements show that existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.