The data acquisition system of the Belle silicon vertex detector (SVD) upgrade

A newly developed data acquisition system (DAQ) for the upgraded silicon vertex detector (SVD2) in the Belle experiment is described. The system consists of 12 PCs connected through PCI I/O boards to 36 flash analog-to-digital converters (FADCs) to read out a system comprising a total of 110 592 strips. It is designed to cope with the increased number of readout channels and the maximum trigger rate of 1 kHz, foreseen in the future operation with higher beam currents. A measurement of the system performance using sparsification algorithm we have developed yields a 1.3-kHz readout rate for a 5% occupancy with less than 5% dead time, which satisfies the requirements on the maximum trigger rate.