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Performance and area modeling of complete FPGA designs in the presence of loop transformations | IEEE Journals & Magazine | IEEE Xplore

Performance and area modeling of complete FPGA designs in the presence of loop transformations


Abstract:

Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration c...Show More

Abstract:

Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to quickly understand the Impact and interaction of the transformations. In this paper, we present a combined analytical performance and area modeling approach for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of computations. Our preliminary results reveal that our modeling is very accurate, being therefore amenable to be used in a compiler tool to quickly explore very large design spaces.
Published in: IEEE Transactions on Computers ( Volume: 53, Issue: 11, November 2004)
Page(s): 1420 - 1435
Date of Publication: 30 November 2004

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