Performance and area modeling of complete FPGA designs in the presence of loop transformations

Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to quickly understand the Impact and interaction of the transformations. In this paper, we present a combined analytical performance and area modeling approach for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of computations. Our preliminary results reveal that our modeling is very accurate, being therefore amenable to be used in a compiler tool to quickly explore very large design spaces.

1 Introduction

Common digital image and signal processing algorithms are structured as a sequence of localized operators (e.g., gradient or min/max) over overlapping blocks of data, typically organized as windows. Given the natural n-dimensional arrangement of the data associated with these algorithms, these window-based computations are naturally expressed in tight loop nests in popular imperative languages such as C. As operators in these algorithms tend to exhibit substantial amounts of instruction level parallelism and the potential for customized implementation (e.g., specific arithmetic formats and/or operations), they are natural candidates for efficient implementation in hardware using Field-Programmable-Gate-Arrays (FPGA) devices.