A digital phase lock loop for VLSI telecommunication applications

The authors describe the design and simulation results for two versions of a digital phase lock loop (DPLL). One version uses a simple random walk filter, whereas the second version uses a simple adaptive scheme to extend the lock frequency range without degrading the phase resolution. Both versions of the DPLL have been successfully simulated using the logic simulator SILOS. The architecture for the adaptive version of the DPLL is shown together with a portion of the simulation timing diagram for the adaptive DPLL just prior to and after lock-in.<
>