Gate dielectric breakdown: A focus on ESD protection

The challenge of electrostatic discharge (ESD) design is that as scaling continues and operating voltages are lowered, the interface to the outside world and therefore the ESD specifications remain the same. Moreover, as has been highlighted by Duvvury et al. (1996), the first breakdown voltage for snapback of a transistor and the median breakdown voltage of the gate dielectric are converging, making it difficult to ensure the robustness of gate dielectrics in an ESD event. This is particularly true for 1V I/O's in high-speed, high-performance applications, where transistor gates may be directly connected to an external pin or NFETs may be used as compact decoupling capacitors between VDD and VSS, exposing the thin gate dielectric to ESD stress. The ESD protection and interconnects can both contribute voltage drops during an ESD pulse, and their sum must not be higher than the voltage which a dielectric can withstand. Especially alarming is the fact that in the sub-2nm regime, significant statistical variation exists as well as a dependence on area for dielectric breakdown. A vast knowledge base exists for oxide breakdown in the long time-scale, and a few publications have addressed short time-scales. For the most part, studies which described breakdowns at short times have used methodology developed for thicker oxides. In the case of thinner oxides or oxynitrides, the voltage acceleration is no longer 1/E, the dielectric breakdown voltage depends sensitively on the dielectric area, and small differences in thickness have a significant effect on the dielectric breakdown voltage. Therefore, the purpose of this paper is to study the relevance of long time-scale TDDB data in predicting the response to short time-scale ESD events, especially for sub-2nm dielectrics in both NFETS and PFETS.