A 0.13-/spl mu/m CMOS serializer for data and trigger optical links in particle physics experiments

A 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-/spl mu/m CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-/spl Omega/ line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B/10 B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 yr. This paper describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and bit-error rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test beds.