A 1.2V low leakage low cost 90 nm CMOS wireless technology with a 60 nm transistor gate length

In this paper, we have demonstrated a low-leakage low-cost 90 nm technology with a 60 nm gate length for high performance operation by using 193 nm strong-phase-shift lithography, nitrided gate oxide, aggressively scaled MDD junctions and 6-level Cu/low-k interconnects.