The coincidence matrix ASIC of the level-1 muon barrel trigger of the ATLAS experiment

The ATLAS barrel level-1 muon trigger processes hit information from the resistive plate chamber detector, identifying candidate muon tracks and assigning them to a programmable p/sub T/ range and to a unique bunch crossing number. The trigger system uses up to seven detector layers and seeks hit patterns compatible with muon tracks in the bending and nonbending projection. The basic principle of the algorithm is to demand a coincidence of hits in the different chamber layers within a path. The width of the road is related to the p/sub T/ threshold to be applied. The system is split into an on-detector and an off-detector part. The on-detector electronics reduces the information from about 350 k channels to about 400 32-bit data words sent via optical fiber to the so-called sector logic (SL). The off-detector SL electronics collects muon candidates and associates them to detector regions-of-interest of /spl Delta//spl eta//spl times//spl Delta//spl Phi/ of 0.1/spl times/0.1. The core of the on-detector electronics is the coincidence matrix ASIC (CMA), which fulfils both the trigger algorithm and the readout of the RPC detector. Each CMA is able to process and readout 192 RPC strips from as many as four detector layers. In order to keep the full level-1 system latency below 2 /spl mu/s, the CMA has to find candidate muon tracks with a latency of a few 25 ns bunch crossing periods. The readout part of the CMA is able to time tag incoming RPC hits with a time interpolator running at the trigger pipeline frequency of 320 MHz and to send the data to the readout system via a serial link. The design of the trigger system and the performances of the ASIC, based on a CMOS 0.18 /spl mu/m technology, are presented.