Impact of CMOS device scaling in ASICs on radiation immunity

Roadmaps for CMOS device technology has shown fast pace scaling in recent years. Mainstream CMOS devices have been produced with feature sizes between 0.1 and 0.25 /spl mu/m since the year 2000 and the so called "fundamental limit" will be reached around the year 2014. This paper reviews the effects of radiation on deep submicron CMOS devices and techniques to harden ASICs against these effects for applications in the space environment, emphasizing the impact of device scaling according to the ITRS roadmap. Radiation effects include traditional ones, such as total ionization dose effects, single-event upset and latchup, as well as newer effects such as hard-errors induced by heavy ions microdoses, gate-rupture and ion-triggered channeling.