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Architectures and VLSI implementations of the AES-Proposal Rijndael | IEEE Journals & Magazine | IEEE Xplore

Architectures and VLSI implementations of the AES-Proposal Rijndael


Abstract:

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption an...Show More

Abstract:

Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decryption process. They reduce the required hardware resources and achieve high-speed performance. Their design philosophy is completely different. The first uses feedback logic and reaches a throughput value equal to 259 Mbit/sec. It performs efficiently in applications with low covered area resources. The second architecture is optimized for high-speed performance using pipelined technique. Its throughput can reach 3.65 Gbit/sec.
Published in: IEEE Transactions on Computers ( Volume: 51, Issue: 12, December 2002)
Page(s): 1454 - 1459
Date of Publication: 06 January 2003

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