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Analysis and Design of RF CMOS Attenuators
Dogan, H.; Meyer, R.G.; Niknejad, A.M.;
Solid-State Circuits, IEEE Journal of
Volume 43,
Issue 10,
Oct. 2008
Page(s):2269
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2283
Abstract:
Attenuators are analyzed for their minimum Insertion Loss (IL), maximum attenuation and source-load matching performance. These results are used to make trade-offs in the design of a CMOS attenuator with wide dynamic range, designed and fabricated in a 0.13 mum CMOS process. The design employs two non-identical cascaded T-stages that are activated consecutively to improve linearity. The design operates in the frequency band of DC-2.5 GHz with 0.9-3.5 dB insertion loss and 42 dB maximum attenuation in the entire frequency range. Worst case S11 is - 8.2 dB across the frequency band. The design achieves an IIP3 of + 20 dBm at mid-attenuation.
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