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Design of Adaptive Deblocking Filter for H.264/AVC Decoder SOC
Kun, Yang; Chun, Zhang; Zhihua, Wang;
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
4-7 Dec. 2006
Page(s):109
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112
Abstract:
Design of adaptive deblocking filter is proposed in this paper. To realize real-time implementation, a FILTER unit that can process 8 pixels beside an edge simultaneously is applied in this design to increase the filtering efficiency, and local memory is used to store all intermediate data generated by the FILTER to reduce the access to system bus. The filter makes every 4times4 sample block pipelined through the process units, and achieves an efficiency of 80% for both FILTER unit and bus access unit. It can fulfil filtering process for a CIF picture in 95k clock cycles. The proposed design is part of a H.264/AVC decoder SOC, which has DMA ability to free the RISC of the decoder from data moving. The H.264/AVC decoder is fabricated in 0.18-mum CMOS process. The die size is 4.8mm times 4.8mm and it can achieve 100MIPS performance
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