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A noise optimization technique for integrated low-noise amplifiers
Jung-Suk Goo; Hee-Tae Ahn; Ladwig, D.J.; Zhiping Yu; Lee, T.H.; Dutton, R.W.;
Solid-State Circuits, IEEE Journal of
Volume 37,
Issue 8,
Aug. 2002
Page(s):994
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1002
Abstract:
Based on measured four-noise parameters and two-port noise theory, considerations for noise optimization of integrated low-noise amplifier (LNA) designs are presented. If arbitrary values of source impedance are allowed, optimal noise performance of the LNA is obtained by adjusting the source degeneration inductance. Even for a fixed source impedance, the integrated LNA can achieve near NFmin by choosing an appropriate device geometry along with an optimal bias condition. An 800 MHz LNA has been implemented in a standard 0.24 μm CMOS technology. The amplifier possesses a 0.9 dB noise figure with a 7.1 dBm third-order input intercept point, while drawing 7.5 mW from a 2.0 V power supply, demonstrating that the proposed methodology can accurately predict noise performance of integrated LNA designs.
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