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A 7-GHz 1.8-dB NF CMOS low-noise amplifier
Fujimoto, R.; Kojima, K.; Otaka, S.;
Solid-State Circuits, IEEE Journal of
Volume 37,
Issue 7,
July 2002
Page(s):852
-
856
Abstract:
A 7-GHz low-noise amplifier (LNA) was designed and fabricated using 0.25-μm CMOS technology. A cascode configuration with a dual-gate MOSFET and shielded pads were adopted to improve the gain and the noise performance. The effects of the dual-gate MOSFET and the shielded pads are discussed quantitatively. An associated gain of 8.9 dB, a minimum noise figure of 1.8 dB, and an input-referred third-order intercept point of +8.4 dBm were obtained at 7 GHz. The LNA consumes 6.9 mA from a 2.0-V supply voltage. These measured results indicate the feasibility of a CMOS LNA employing these techniques for low-noise and high-linearity applications at over 5 GHz
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