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Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits
Badaroglu, M.; van Heijningen, M.; Gravot, V.; Compiet, J.; Donnay, S.; Gielen, G.G.E.; De Man, H.J.;
Solid-State Circuits, IEEE Journal of
Volume 37,
Issue 11,
Nov. 2002
Page(s):1383
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1395
Abstract:
This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 μm CMOS process on an EPI-type substrate with 10 Ωcm EPI resistivity and 4 μm EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.
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