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Clock and data recovery IC for 40-Gb/s fiber-optic receiver
Georgiou, G.; Baeyens, Y.; Young-Kai Chen; Gnauck, A.H.; Gropper, C.; Paschke, P.; Pullela, R.; Reinhold, M.; Dorschky, C.; Mattia, J.-P.; von Mohrenfels, T.W.; Schulien, C.;
Solid-State Circuits, IEEE Journal of
Volume 37,
Issue 9,
Sep 2002
Page(s):1120
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1125
Abstract:
The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.
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