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    Computer aided partitioning for design of parallel testable VLSI systems

    Jose, D. ; Kumar, P.N. ; Saravakanthan, L. ; Dheeraj, R.
    Advances in Computing, Communications and Informatics (ICACCI), 2013 International Conference on

    DOI: 10.1109/ICACCI.2013.6637376
    Publication Year: 2013 , Page(s): 1363 - 1366

    IEEE Conference Publications

    Design automation is a challenge for tool designers, due to increasing complexity of building VLSI circuits with molecular and nano-scale precision. Recent emerging complex problems in the field of VLSI design can be easily solved through the divide and conquer approach using partitioning methods. Although, partitioning problem has major importance in the field of VLSI design automation, it is treated with a testing perspective in this paper. This facilitates to address the reliability and testability issues of VLSI systems during the early product development stages. An automated VLSI design tool for partitioning combinational CMOS circuits that can create parallel testable VLSI circuits, is developed and discussed. This computer aided tool can optimize the design constraints of test time and hardware overhead for design-for-testability (DFT) by an exploration of the solution search space. After partitioning and optimization, a considerable reduction in the length of test vectors is obtained. View full abstract»

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    VLSI signal processing oriented segmentation based serial parallel multiplier

    Vandana, A.R.
    Devices, Circuits and Systems (ICDCS), 2012 International Conference on

    DOI: 10.1109/ICDCSyst.2012.6188664
    Publication Year: 2012 , Page(s): 451 - 455

    IEEE Conference Publications

    In this paper a novel VLSI SP oriented architecture for implementation of serial parallel Multipliers (SPM) is proposed. The VLSI oriented multiplier is based on a segmentation technique of SPM and the conventional full adders are replaced by low power full adder. In this paper two architectures namely Segmented Based SPM, Folded VLSI oriented segmented based SPM are compared for power and area. The proposed VLSI SP oriented architecture achieves higher throughput and less area compared to the segmentation based serial parallel multiplier proposed [1]. The proposed VLSI SP oriented architecture permits the optimization of the area, speed and power. View full abstract»

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    Personal-computer based digital and analog VLSI design laboratories

    Leigh, W.B.
    Microelectronic Systems Education, 1997. MSE '97. Proceedings., 1997 IEEE International Conference on

    DOI: 10.1109/MSE.1997.612532
    Publication Year: 1997 , Page(s): 25 - 27

    IEEE Conference Publications

    A goal in the Electrical Engineering Division at Alfred has been to expand the VLSI curriculum to a pyramid of courses structured to teach the students VLSI design from several aspects. Emphasis of the new VLSI design curriculum is on design methodologies and specific applied design paradigms. The VLSI tools are used solely on personal computers, and the courses are designed so the instructor can teach the laboratories with little or no computer technical assistance. The laboratories are designed so that 1-2 faculty can be used with help from workstudy students. The introductory course is offered to both juniors and seniors. Students taking the course in their junior year have the advantage of more detailed VLSI design experience in their senior year. Expansion of VLSI design increases the student's proficiency in analog design using full custom design and digital design using synthesis tools and Verilog HDL. In the VLSI special topics course, student work as a single group on a design problem and emphasis is on design methodologies, time to market strategies, design for testability and design for quality View full abstract»

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    Optoelectronic-VLSI: photonics integrated with VLSI circuits

    Krishnamoorthy, A.V. ; Goossen, K.W.
    Selected Topics in Quantum Electronics, IEEE Journal of

    Volume: 4 , Issue: 6
    DOI: 10.1109/2944.736073
    Publication Year: 1998 , Page(s): 899 - 912
    Cited by:  Papers (54)  |  Patents (3)

    IEEE Journals & Magazines

    Optoelectronic-VLSI (OE-VLSI) technology represents the intimate integration of photonic devices with silicon VLSI electronics. We review the motivations and status of emerging OE-VLSI technologies and examine the performance of OE-VLSI technology versus conventional wire-bonded OE packaging. The results suggest that OE-VLSI integration offers substantial power and speed improvements even when relatively small numbers of photonic devices are driven with commodity complementary metal-oxide-semiconductor logic technologies View full abstract»

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    Qualitative comparison of MQW modulator and VCSEL based OE-VLSI: a systems perspective

    Lentine, A.L.
    Lasers and Electro-Optics Society Annual Meeting, 1997. LEOS '97 10th Annual Meeting. Conference Proceedings., IEEE

    Volume: 2
    DOI: 10.1109/LEOS.1997.645266
    Publication Year: 1997 , Page(s): 83 - 84 vol.2

    IEEE Conference Publications

    A particularly useful platform for two dimensional optical interconnects is Optoelectronic VLSI (OE-VLSI). OE-VLSI consists of the hybrid integration of (at least) thousands of optical sources or modulators, optical detectors, and silicon VLSI circuitry. While a VCSEL based OE-VLSI platform is currently desired by many working in the field, a MQW modulator based platform is currently commercially available with Gb/s I/O speeds, up to 65 k optical I/O and potential aggregate I/O bandwidths exceeding a terabit per second. VCSEL based OE-VLSI has recently achieved the integration of 256 VCSELs on a silicon driver, with only one VCSEL operating concurrently, and no integrated detectors. The technological challenges in manufacturing a usable VCSEL based OE-VLSI platform are formidable, yet, the desire by many for this technology over the modulator based technology remains. Quantitative analysis have been performed that compare the overall dissipation of VCSEL and modulator based systems. In this talk, I will examine, qualitatively, the issues of building systems with both technologies, assuming of course, that a VCSEL based OE-VLSI platform will one day exist View full abstract»

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    An error decoder for the Compact Disc player as an example of VLSI programming

    Kessels, J. ; van Berkel, K. ; Burgess, R. ; Roncken, M. ; Schalij, F.
    Design Automation, 1992. Proceedings., [3rd] European Conference on

    DOI: 10.1109/EDAC.1992.205896
    Publication Year: 1992 , Page(s): 69 - 74
    Cited by:  Papers (8)

    IEEE Conference Publications

    Using a programming language for VLSI design, called Tangram, they design a fast and simple VLSI circuit for error decoding in the Compact Disc player. The derivation of the design is straightforward and the result is succinctly expressed in less than one page of Tangram text. All design decisions are based merely on algorithmic and architectural considerations. No particular VLSI knowledge is needed and, therefore, the exercise demonstrates that Tangram allows system designers to design VLSI circuits. The exercise also shows that in a VLSI programming language special language constructs are essential to obtain efficient designs View full abstract»

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    Mapping tensor products onto VLSI networks with reduced I/O

    Elnaggar, A. ; Alnuweiri, H.M. ; Ito, M.R.
    VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

    DOI: 10.1109/GLSV.1994.289978
    Publication Year: 1994 , Page(s): 150 - 155
    Cited by:  Papers (3)

    IEEE Conference Publications

    This paper presents a methodology for designing folded VLSI networks for implementing tensor-product forms. Using tensor-products leads to very efficient expressions for a large number of computations in digital signal processing and matrix arithmetic. The resulting networks can trade-off total time delay with I/O bandwidth and chip area. The main goal is to parametrize the VLSI architecture so that it can be implemented under various packaging constraints including the available number of I/O pins, available chip-area, and certain restrictions on maximum wire length. Our methods result in folded VLSI networks with optimal AT2 trade-off for digital filtering and multidimensional transforms, where A is the total area of the VLSI circuit (or chip) and T is its total time delay View full abstract»

  • Freely Available from IEEE

    Proceedings IEEE Computer Society Annual Symposium on VLSI. New Trends and Technologies for VLSI Systems Design. ISVLSI 2003


    VLSI, 2003. Proceedings. IEEE Computer Society Annual Symposium on

    DOI: 10.1109/ISVLSI.2003.1183342
    Publication Year: 2003

    IEEE Conference Publications

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    Enhancement of competence in microelectronics technology through incorporation of VLSI design and fabrication courses in engineering curriculum

    Prasad, K.
    University/Government/Industry Microelectronics Symposium, 1989. Proceedings., Eighth

    DOI: 10.1109/UGIM.1989.37321
    Publication Year: 1989 , Page(s): 137 - 140
    Cited by:  Papers (2)

    IEEE Conference Publications

    The offering of state-of-the-art courses in VLSI design and fabrication, especially at the undergraduate level, at ULowell (University of Lowell) is discussed. ULowell recognizes the multidisciplinary nature of this field, and thereby encourages its professors to take courses in semiconductor and VLSI-related fields, and to send them to participate in appropriate workshops, seminars, and conferences through professional development support. Although ULowell puts adequate emphasis on material innovation and semiconductor device development, it is recognized that the real challenge is in system design, making use of the most modern devices. It is with this view that system integration, design, and fabrication are taught in great detail, so that the challenge of enhancing the national competence in chip production and manufacturing of all sorts of systems could be met. In order to meet R&D challenges of VLSI technology, a VLSI design course, an advanced VLSI design course, and a VLSI fabrication course were also initiated at the graduate level View full abstract»

  • Freely Available from IEEE

    Proceedings. VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks (Cat. No.89CH2704-5)


    CompEuro '89., 'VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks', Proceedings.

    DOI: 10.1109/CMPEUR.1989.93506
    Publication Year: 1989

    IEEE Conference Publications

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    The cylinder switch: an architecture for a manageable VLSI giga-cell switch

    Monderer, B. ; Pacifici, G. ; Zukowski, C.
    Communications, 1990. ICC '90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on

    DOI: 10.1109/ICC.1990.117143
    Publication Year: 1990 , Page(s): 567 - 571 vol.2
    Cited by:  Papers (2)

    IEEE Conference Publications

    A cell switch architecture is proposed that provides resource allocation and buffer management features in the hardware. The cylinder switch system is specifically designed to take advantage of the properties of VLSI, and high-performance structures only available in VLSI can naturally be applied. The switch fabric is constructed from ring buffer/multiplexer VLSI modules that form a cylinder buffer. The buffers of this system are completely shared among the input channels. Multicasting, slot reservation in the buffer and on the output channel, class and priority control, and packet reordering are some of the feature that can be utilized. Both analog and digital observation and control can be utilized. The switch capacity using current VLSI technology could be in the tens of gigabits for a 100×100-channel switch. In addition to analytical and simulation studies, a prototype VLSI chip is being implemented for testing the ideas View full abstract»

  • Freely Available from IEEE

    IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.91CH3040-3)


    Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

    DOI: 10.1109/ICCD.1991.139994
    Publication Year: 1991

    IEEE Conference Publications

  • Freely Available from IEEE

    Proceedings. IEEE Computer Society Annual Symposium on VLSI


    VLSI, 2005. Proceedings. IEEE Computer Society Annual Symposium on

    DOI: 10.1109/ISVLSI.2005.40
    Publication Year: 2005

    IEEE Conference Publications

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    Real-time computing of optical flow using adaptive VLSI neuroprocessors

    Wai-Chi Fang ; Sheu, B.J. ; Lee, J.-C.
    Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings, 1990 IEEE International Conference on

    DOI: 10.1109/ICCD.1990.130180
    Publication Year: 1990 , Page(s): 122 - 125

    IEEE Conference Publications

    The multilayer stochastic neural network and its associated VLSI array neuroprocessors are presented for VLSI optical flow computing. This network is well-suited to VLSI implementation due to the high parallelism and local connectivity. Instead of using deterministic scheme, a stochastic decision rule implemented with electronic annealing techniques is used to search optimal solutions. VLSI array neuroprocessor architecture is proved to be an effective supercomputing hardware for real-time optical flow applications. A prototype 25-neuron chip for this VLSI array neuroprocessors (called a velocity-selective hyperneuron chip) has been implemented using MOSIS 2-μm CMOS technology. A real-time optical flow machine is feasible by using arrays of hyperneuron chips View full abstract»

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    Introducing VLSI computer-aided design into the EE curriculum: a case study

    O'Keefe, M.T. ; Lindenlaub, J. ; Bass, S.C. ; Wahlen, T.P.
    Education, IEEE Transactions on

    Volume: 32 , Issue: 3
    DOI: 10.1109/13.34154
    Publication Year: 1989 , Page(s): 226 - 236
    Cited by:  Papers (8)

    IEEE Journals & Magazines

    The authors describe a case study at Purdue University's School of Electrical Engineering in the successful integration of VLSI CAD (computer-aided design) into both the undergraduate and graduate curriculum. The courses in VLSI chip design use the Manassas VLSI Interactive System for Automation (MVISA), a CAD program that implements all stages in the VLSI design process including logic entry (schematic capture), logic simulation, timing analysis, design rule checking, placement of cells, and automatic and manual wiring. The successful integration was due to several factors, including university-industry-government cooperation; the development of a comprehensive set of interactive tutorials and notes describing the lab procedures and VLSI issues considered in the class; and a coherent, structured approach to teaching system design as well as the use of CAD tools in this process. Modern educational techniques, including computer-aided instruction and videotaped lectures on VLSI, also played a part in the development of the CAD courses View full abstract»

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    Noise margin constraints for interconnectivity in deep submicron low power and mixed-signal VLSI circuits

    Li-Rong Zheng ; Tenhunen, H.
    Advanced Research in VLSI, 1999. Proceedings. 20th Anniversary Conference on

    DOI: 10.1109/ARVLSI.1999.756043
    Publication Year: 1999 , Page(s): 123 - 136
    Cited by:  Papers (2)  |  Patents (1)

    IEEE Conference Publications

    The continually growth in density and complexity of integrated circuits gives a difficult challenge in wireability of deep submicron VLSI circuits, particularly the advanced low power and mixed-signal ICs, where the interconnections have been seriously limited by the noise coupling problem. In this paper, we analyse the interconnectivity of advanced deep submicron low power and mixed-signal VLSI circuits under noise margin constraints. We show that noise margin constraint for signal coupling will restrict interconnect density as well as process technology options. The maximum interconnectivity, process technology options, and physical delay etc. are analysed against the noise margin constraints, for both with and without shielding wire cases. The optimal geometry and wirings for both local and global interconnects are studied with respect to noise margin, physical delay, and interconnect cross section area etc. Constraint for maximum available interconnectivity is demonstrated for interconnect wire geometry characteristics of advanced deep submicron CMOS processes. Our study reveals that, in advanced deep submicron VLSI circuit designs, interconnects should be separated functionally. Different geometries and wiring types and perhaps different fabrication flows and processes should be utilized in one chip. Some of the interconnect layers will be thus heavily dedicated such as some for local interconnects, some for intramodule interconnects, some for global wiring, and some for ground and power etc., all with optimal geometries View full abstract»

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    Three-dimensional pipeline clock network design with multi-layer processor chip and multi-clock VLSI system

    Yun Yang
    SoC Design Conference (ISOCC), 2013 International

    DOI: 10.1109/ISOCC.2013.6863975
    Publication Year: 2013 , Page(s): 019 - 022

    IEEE Conference Publications

    This paper proposes the pipeline clock network design for recent three-dimensional (3D) VLSI system. The multi-layer processor chip can be connected by Through-Silicon Via (TSV) tunnels. The multi-clock VLSI system can also enhance whole VLSI system performance for better design flexibility. The pipeline clock network is determined by inserted buffer control. Different size buffers in different layers can realize fast system operation and zero-skew clock signals. Whole VLSI processor speed can be increased rapidly, and 3D chip size can also be reduced greatly by 3D pipeline clock network design. System clock routing efficiency can also be improved because 3D clock tree can avoid most parts of the obstacle elements. Experimental results can be used to prove that 3D pipeline clock network has better performance with fast operation speed and small routing length. VLSI system power can be reduced because of minimal routing distance in 3D network design. View full abstract»

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    A fast algorithm for VLSI net extraction

    Lopez, M.A. ; Janardan, R. ; Sahni, S.
    Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on

    DOI: 10.1109/ICCAD.1993.580176
    Publication Year: 1993 , Page(s): 770 - 774
    Cited by:  Papers (1)

    IEEE Conference Publications

    Net extraction is crucial in VLSI design verification. Current algorithms for net extraction do not exploit the fact that the number, c, of different orientations of the line segments or polygon edges in a practical VLSI mask design is small relative to the number, n, of segments or edges. Instead, they rely on computing all intersections in the input and hence take time that is at least proportional to the number of intersections. In this paper we develop a simple and practical algorithm for net extraction that runs in O(cn log n) time and O(n) space, which is optimal for fixed c. Experiments indicate that the algorithm will generally outperform existing algorithms on practical VLSI designs. We expect that the techniques presented will be useful in other VLSI CAD problems that operate with restricted orientation geometries. View full abstract»

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    Fault Emulation for Dependability Evaluation of VLSI Systems

    de Andres, D. ; Ruiz, J.C. ; Gil, D. ; Gil, P.
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

    Volume: 16 , Issue: 4
    DOI: 10.1109/TVLSI.2008.917428
    Publication Year: 2008 , Page(s): 422 - 431
    Cited by:  Papers (8)

    IEEE Journals & Magazines

    Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inject a wide set of faults representative of deep-submicrometer technology, like stuck-at, bit-flip, pulse, indetermination, stuck-open, delay, short, open-line, and bridging, using the best suitable FPGA- based technique. This paper also sets some basic guidelines for comparing VLSI systems in terms of their availability and safety, which is mandatory in mission and safety critical application contexts. This represents a step forward in the dependability benchmarking of VLSI systems and towards the definition of a framework for their evaluation and comparison in terms of performance, power consumption, and dependability. View full abstract»

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    Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling

    Crupi, F. ; Alioto, M. ; Franco, J. ; Magnone, P. ; Kaczer, B. ; Groeseneken, G. ; Mitard, J. ; Witters, L. ; Hoffmann, T.Y.
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

    Volume: 20 , Issue: 8
    DOI: 10.1109/TVLSI.2011.2159870
    Publication Year: 2012 , Page(s): 1487 - 1495
    Cited by:  Papers (4)

    IEEE Journals & Magazines

    In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high- κ/metal gate stack, as well as on 45-nm Si pMOSFETs with identical gate stack for comparison. In the reference SiGe technology, an innovative technological solution is adopted that limits the SiGe material only to the channel region. The resulting SiGe device merges the higher speed of the Ge technology with the lower leakage of the Si technology. Appropriate circuit- and system-level metrics are introduced to identify the advantages offered by SiGe technology in VLSI circuits. Analysis is performed in the context of next-generation VLSI circuits that fully exploit circuit- and system-level techniques to improve the energy efficiency through aggressive voltage scaling, other than low-leakage techniques. Analysis shows that the SiGe technology has more efficient leakage-delay and dynamic energy-delay trade-offs at nominal supply, compared to Si technology. Moreover, it is shown that the traditional analysis performed at nominal supply actually underestimates the benefits of SiGe pMOSFETs, since the speed advantage of SiGe VLSI circuits is further emphasized at low voltages. This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits, thereby making SiGe devices a very promising alternative to Si transistors in next-generation VLSI systems. View full abstract»

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    Optical interconnects for neural and reconfigurable VLSI architectures

    Fey, D. ; Erhard, W. ; Gruber, M. ; Jahns, J. ; Bartelt, H. ; Grimm, G. ; Hoppe, L. ; Sinzinger, S.
    Proceedings of the IEEE

    Volume: 88 , Issue: 6
    DOI: 10.1109/5.867697
    Publication Year: 2000 , Page(s): 838 - 848
    Cited by:  Papers (14)

    IEEE Journals & Magazines

    The increasing transistor density in very large-scale integrated (VLSI) circuits and the limited pin member in the off-chip communication lead to a situation described as interconnect crisis in micro-electronics. Optoelectronic VLSI (OE-VLSI) circuits using short-distance optical interconnects and optoelectronic devices like microlaser, modulator, and detector arrays for optical off-chip sending and receiving offer a technology to overcome this crisis. However, in order to exploit efficiently the potential of thousands of optical off-chip interconnects, an appropriate VLSI architecture is required. We show for the example of neural and reconfigurable VLSI architectures that fine-grain architectures fulfill these requirements. An OE-VLSI circuit realization based on multiple quantum-well modulators functioning as two-dimensional (2-D) optical input/output (I/O) interface for the chip is presented. Due to the parallel optical interface, and improvement of two to three orders of magnitude in the throughput performance is possible compared to all-electronic solutions. For the optical interconnects, a planar-integrated free-space optical system has been designed leading to an optical multichip module. Such a system has been fabricated and experimentally characterized. Furthermore, we designed an manufactured fiber arrays, which will be the core element for a convenient test station for the 2-D optoelectronic I/O interface of OE-VLSI circuits. View full abstract»

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    Efficient external memory segment intersection for processing very large VLSI layouts

    Sharathkumar, R. ; Vinaykumar, M.T.C. ; Maheshwari, P. ; Gupta, P.
    Circuits and Systems, 2005. 48th Midwest Symposium on

    DOI: 10.1109/MWSCAS.2005.1594207
    Publication Year: 2005 , Page(s): 740 - 743 Vol. 1
    Cited by:  Papers (1)

    IEEE Conference Publications

    One fundamental problem that arises in VLSI layout analysis and verification is the segment intersection problem: given a set of segments in the plane, find all pairwise intersections. This problem has been widely studied in the Computational Geometry. One problem with processing large VLSI layouts is that the data to be processed may be far too massive to fit in main memory. When dealing with data sets of sizes exceeding main memory, communication between the fast internal memory and the slow external memory is often the performance bottleneck and algorithms and data structures designed under the assumption of a single level of memory may be meaningless. External-memory algorithms try to optimize performance by taking into account disk accesses. One can certainly use the standard main memory algorithms for data that reside on disk but their performance is often considerably below the optimum because there is no control over how the operating system performs disk accesses. On demand thrashing can be high thus resulting in an increase in response time. Although a lot of research has been done in the recent past on efficient external-memory algorithms and data structures, such work in the area of VLSI computer-aided design is limited. We have designed and implemented a practical external-memory algorithm for reporting all intersecting pairs amongst a set of orthogonal segments. The key to our success is that we take advantage of the fact that real data sets from VLSI applications tend to obey the so-called "square-root" rule, i.e. in a set of TV line segments, the expected number of line segments intersecting a horizontal or vertical scanline in a VLSI layout is O(radic N), a fact ignored by known external-memory algorithms. Another factor that is crucial to our success is that other algorithms stores the data structures in external memory requiring I/O to access them. We reduce such disk accesses by using a clever storage scheme. Our algorithm outperforms not only a - - standard in-memory algorithm but also an existing external-memory algorithm for segment intersection reporting View full abstract»

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    A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching

    Yungseon Eo ; Seongkyun Shin ; Eisenstadt, W.R. ; Jongin Shim
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

    Volume: 23 , Issue: 9
    DOI: 10.1109/TCAD.2004.831571
    Publication Year: 2004 , Page(s): 1321 - 1337
    Cited by:  Papers (11)  |  Patents (1)

    IEEE Journals & Magazines

    In today's high-speed/high-density very large scale integrated (VLSI) circuit designs with coupled interconnect lines, signal transients are strongly correlated with the input switching patterns. Signal-delay variations due to the input-switching patterns may be more than ±50% of the delay of an isolated single line. Thus, blind static timing-analysis techniques without consideration of the detailed switching effects may not be accurate enough to meet tight timing margins for today's deep submicron (DSM)-based VLSI circuits. In this paper, the signal-transient responses of multicoupled interconnect lines due to various input-switching patterns are analyzed in terms of the effective capacitances and effective inductances. Thereby, the critical delay line of multicoupled interconnect lines is decoupled into an effective single-isolated line. With the proposed novel decoupling technique for multicoupled interconnect lines, the accurate dynamic delay of strongly coupled interconnect lines can be readily determined with physical layout information. For example, in switching patterns, the paper shows that the signal delays calculated by using the effective single-line models have excellent agreement with SPICE simulations using the generic coupled interconnect circuit models. That is, the accuracy for both RC-dominant lines and RLC lines is within 10% error (but often within 5% error). Thus, without any significant modification of existing IC computer-aided design frameworks, the technique can be directly as well as usefully employed for accurate timing verification of DSM-based VLSI designs. View full abstract»

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    Design and VLSI implementation of an address generation coprocessor

    Hulina, P.T. ; Coraor, L.D. ; Kurian, L. ; John, E.
    Computers and Digital Techniques, IEE Proceedings -

    Volume: 142 , Issue: 2
    DOI: 10.1049/ip-cdt:19951605
    Publication Year: 1995 , Page(s): 145 - 151
    Cited by:  Papers (2)  |  Patents (2)

    IET Journals & Magazines

    Most applications of general purpose VLSI processors are developed using high level languages. In these languages, information is generally handled in a structured form. Compilers generate a considerable amount of code to navigate through the data structures and considerable processing time is spent performing address calculations required to access the data structures. An alternative to software address generation, a hardware memory reconfiguring unit or an address generation coprocessor is presented. To demonstrate the VLSI feasibility of the designed device, it is implemented in VLSI using the Octtool suite of tools. The tools used and the implementation procedure are described. VLSI design aspects such as regularity, modularity, scalability, etc. are discussed. The performance of the device is evaluated using assembly language programs that implement popular signal processing algorithms such as convolution, correlation, FFT and matrix multiplication. A system with the address generation unit exhibits a speed up of between approximately 1.5 and 2.5 View full abstract»

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    Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

    Semenov, O. ; Pradzynski, A. ; Sachdev, M.
    Semiconductor Manufacturing, IEEE Transactions on

    Volume: 15 , Issue: 1
    DOI: 10.1109/66.983439
    Publication Year: 2002 , Page(s): 9 - 18
    Cited by:  Papers (14)

    IEEE Journals & Magazines

    In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield View full abstract»

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