A new Class-K* audio amplifier with high-power efficiency and high fidelity is integrated in a 0.35-μm CMOS process. It proposes a new topology connected Class-D amplifier with fast-switching charge-dump (FSCD) amplifier in parallel. The integration of the amplifier requires neither analog buffer amplifier nor a complex compensation circuit needed in hybrid audio amplifier (Class-K). The FSCD amplifier composed of comparators and switches works at a high-switching frequency in order to absorb the distortion caused by Class-D amplifier switching. Thus, this assists the audio amplifier to have good linearity under switching operation. With the proposed topology, the audio amplifier has a flat frequency response with - 3-dB bandwidth of 60 KHz and is capable of delivering up to 257 mW into 4.1-Ω load with maximum efficiency of 81%. A typical total harmonic distortion plus noise (THD+N) is less than 0.1% at the power level over 25 mW within the audio frequency range (20 Hz-20 kHz), and the minimum THD+N is 0.025% with the audio input frequency of 1 kHz at the output power of 114 mW. View full abstract»

A low power, high PSRR, clock-free, current-controlled class-D audio power amplifier is presented. The proposed audio amplifier utilizes integral sliding mode control (ISMC) to ensure robust operation and to minimize the steady-state error. This architecture has two feedback loops: an outer voltage loop that minimizes the voltage error between the input and output audio signals, and an inner current loop that measures the inductor current to track the input signal accurately. The proposed amplifier achieves up to 82 dB of power supply rejection ratio (PSRR), more than 90 dB of signal-to-noise (SNR) ratio over the entire audio band, and total harmonic distortion plus noise (THD+N) as low as 0.02%. A power-supply-induced intermodulation distortion (PS-IMD) of approximately - 90 dBc was measured for an input voltage signal of 2 V_pp at 1 kHz and a sinusoidal power-supply ripple of 300 mV_pp at 217 Hz superimposed on the DC level. The IC prototype's controller consumes 30% less power than those of recently published works. The audio amplifier operates with a 2.7-V single voltage supply and delivers a maximum output power of 410 mW with 84% peak efficiency (η) into an 8 Ω speaker. It was fabricated using 0.5 μm CMOS standard technology, and occupies a total active area of 1.65 mm². View full abstract»

A fast switching charge dump assisted class-D audio amplifier is presented in this paper. To achieve high efficiency and high linearity, the Class-K* audio amplifier consists of the class D amplifier with high efficiency and the proposed charge dump amplifier with high linearity. The charge pump amplifier works at faster switching frequency than class D amplifier so as to compensate the distortion caused by switching of the class-D amplifier. The class-K* audio amplifier implemented in 0.35mum CMOS process shows -71.8 dB THD+N at 1 KHz and a maximum efficiency of 81% at an output power of 257 mW for 4.1Omega load. View full abstract»

Voltage feedback is frequently used in class-D switching audio power amplifiers. This paper discusses the design and implementation of a low-cost filterless class-D, unipolar pulse-width modulation switching audio amplifier having a multi-loop voltage feedback scheme. Classical frequency-compensation techniques are used to design and stabilize the three voltage feedback loops implemented in this application. This design method proves to be a cost-effective solution for designing high-fidelity (hi-fi) audio amplifiers. The cost is reduced because no output filter is used, the required switching frequency is half of the one needed if bipolar PWM was used, and no current sensor is needed for feedback purposes. The output impedance is extremely low due to the reduction of the successive voltage loops, making the amplifier less load dependent. Simulation results show that a total harmonic distortion (THD) of 0.005% can be achieved using this topology, as well as a flat frequency response, free of phase distortion in the audio band. Experimental results show the feasibility of this control scheme, since a THD of 0.05% was achieved with a laboratory prototyped amplifier. A comparison of the performance of this audio amplifier with that of some commercial class-D audio amplifiers, reveals that our design can seriously compete with some of the ICs leading the market at a lower cost. View full abstract»

In this paper a high efficiency Pulse Width Modulation PWM Complementary Metal Oxide Semiconductor CMOS audio power amplifier is proposed. The original idea is based on the difference close-loop feedback technique and the difference pre-amp. Thus, we conceive a rail to rail comparator with a constant gm. This rail-to-rail PWM comparator with hysteresis architecture has been embedded in the audio power amplifier. The simulation results based on the Taiwan Semiconductor Manufacturing Company TSMC 0.18μm CMOS process show that the power efficiency is 85%, the Power Supply Rejection Ratio PSRR is -70 dB, the power supply voltage range is 1.8-3.3V, the Total Harmonic Distortion plus Noise THD+N in 1 kHz input frequency is 0.2%, the quiescent current is 2.7 mA. With the good performance, the audio power amplifier can be applied to various kinds of small and medium power audio amplification system such as DVD, LCD-TV, MP4 and wireless phones. View full abstract»

The switching audio amplifiers are widely used in various portable and consumer electronics due to their high efficiency, but suffers from low audio performances due to inherent nonlinearity. This paper presents an integrated class D audio amplifier with low consumption and high audio performances. It includes a power stage and an efficient control based on sliding mode technique. This monolithic class D amplifier is capable of delivering up to 1 W into 8 Omega load at less 0.01% THD from a 2.3 V power supply voltage in the high fidelity range (20 Hz-20 kHz). The power supply rejection is superior to 70 dB. View full abstract»

This paper proposes a novel topology of a two independent channel switched audio high power amplifier. A three-branch inverter, two high frequency isolation transformers, two output high frequency cycloconverters and two low-pass filters, compose the basic topology. This architecture has the advantage that the inverter middle branch is common to both channels of the amplifier, without compromising the channel independency, and reducing the number of devices. The objective is to obtain a compact, high power density and reliable system. This Single Conversion Stage Amplifier topology integrates in a single unit both the power supply and the D-class amplifier, conferring to the total system direct and more efficient power conversion and compactness due to the component reduction. Since the amplifier outputs are totally isolated, modular operation is possible among several amplifier units or even between the two channels of a same unit. The amplifier output filter specifications could be relaxed because the principle of operation duplicates the equivalent switching frequency. Another advantage is that the output cycloconverters switch with zero voltage, reducing switching losses. The proposed topology is described and analysed, with emphasis in the principle of operation, modulation techniques and design criteria. The experimental results verify the theoretical analysis. View full abstract»

A low-distortion three-stage class-AB audio amplifier is designed to drive a 16-Ω headphone speaker load. High power efficiency is achieved using fully differential internal stages with local common-mode feedback and replica biasing of the output stage. The threshold voltage of nMOS transistors was made comparable to that of pMOS transistors by negatively biasing the p-substrate in order to achieve high linearity. Multiple compensation networks guarantee the stability of the audio amplifier when driving a wide range of capacitive loads from 10 pF to 5 nF. Peak power delivered to the load is measured as 93.8 mW (corresponding to 46.9 mW RMS) with -77.9-dB total harmonic distortion; quiescent power is only 1.43 mW. The power-supply rejection ratio from both ±1.5-V supplies exceeds 63 dB over the entire audio frequency range. The design is implemented in a 0.5-μm CMOS process and occupies 0.34 mm² of area. View full abstract»

In recent years, the introduction of audio switching amplifiers in the audio chain has improved the efficiency, size, and weight of several apparatus. The integration between power supply and amplifier systems appears as the next logical step to achieve further reducing in size, cost and energy consumption. The present paper presents one single stage switching power amplifier and power supply for sub-woofer amplification. It corresponds to a symbiotic choice of a three-level modulation switched audio amplifier with differential filter, feed forward control and a valley-fill circuit. It has high efficiency; very low power supply capacitor values, and minimizes the weight, size, complexity and cost of the reproduction system. The realization of a prototype shows the effectiveness of the proposed solution. View full abstract»

In recent years, class D audio amplifiers are becoming the most feasible solution for low-voltage low- power applications due to their high efficiency property; however, to obtain good linearity for high fidelity systems is still a challenge. This work does not require the triangular carrier signal used in conventional class D audio amplifiers. It is shown that by making use of the sliding mode (SM) control technique along with an extra local feedback loop, the design parameters of a class D audio amplifier can be selected according to the linearity requirements. These techniques are applied in the design of a class D audio amplifier to yield a single-chip low distortion audio amplifier with efficiency above 90% and THD as low as 0.08%. Experimental IC results, using a commercial 0.5- mum CMOS technology verified the theoretical results. View full abstract»

A one-chip integrated circuit (IC) of a 10-W class-D audio power amplifier with very high efficiency using CMOS technology is presented. A mixture of a class D output stage and a bridge tied load (BTL) is the main topology of the proposed amplifier. The new 10-W IC audio power amplifier operates at 12 V with the efficiency of more than 90% and the total harmonic distortion (THD) of 0.1%. The amplifier is implemented in a 4-μm double-metal, single-poly CMOS technology that provides with relatively high voltage (12 V) MOSFETs View full abstract»

This paper presents an audio amplifier that simultaneously has the advantages of digital and analog amplifier. The high efficiency is achieved by the digital amplifier, which is playing a role of dependent current source. The high fidelity is guaranteed by the analog amplifier playing a role of independent voltage source. Experimental results show that the proposed amplifier has 0.005% total harmonic distortion (THD) and around 90% power efficiency at 50 W output View full abstract»

A high-power-supply-rejection-ratio (PSRR), reconfigurable class-AB/D audio power amplifier is designed for direct battery hookup in portable applications. The proposed design employs the on-chip battery voltage tracking common-mode reference (BAVTCMR) generator and the pseudo-differential topology to achieve the high SNR requirement in a hands-free/receiver 2-in-1 loudspeaker. This amplifier can achieve 106 dB/100 dB PSRR at 217 Hz and 1 kHz, respectively. In receiver mode, this design can drive 46 mW into an 8- Ω load. A true 100-dB SNR is also achieved when a global system for mobile communications (GSM) is generating ripple noise on the system power lines. Reconfiguration is implemented by employing the low-noise operational amplifier (opamp) and capacitors in the class-D integrator as the first gain stage and the compensation capacitors, respectively, in a class-AB amplifier. Hence, the hardware redundancy and the design complexity are both minimized. Fabricated with 0.153-μm CMOS technology, 74-dB/76-dB THD are achieved for class-AB and class-D, respectively. More than 90% efficiency is achieved in class-D mode operation. The maximum output power at 1% THD is 1.23 W. The active area of the prototype class-AB/D amplifier is 0.5 mm². View full abstract»

This paper presents the design and development of a pulse-width-modulated (PWM) power MOSFET-based audio amplifier. A natural sampled PWM switching strategy is implemented in the development of the amplifier to reduce its harmonic level and increase its efficiency. IRF510 power MOSFETs are used as the amplifier power switching devices. From the results obtained, it is found that the efficiency of the amplifier can be increased to more than 90% View full abstract»

In this paper, we present a class-H audio amplifier with an H-bridged output stage. System efficiency is improved by producing a voltage envelope that tracks the input audio signal. The tracking envelope is realized by regulating a buck converter internally using voltage and current hysteresis control schemes. The H-bridged class-B output stage is designed to maximize the output swing across the speaker load with little crossover distortion. The proposed design is capable of providing a peak output RMS power of 0.49 W to an 8 Ω speaker load. The entire system is designed and simulated in a 0.18-μm CMOS technology. In simulation, the proposed audio amplifier shows improved power efficiencies and good output linearities with THD less than 0.1% under different input signals. View full abstract»

This paper presents a single-chip digital audio amplifier based on a delta-sigma (/spl Delta//spl Sigma/) modulator and a power efficient switching (class-D) output-stage without intermediate filtering. Fabricated in a 0.18/spl mu/m standard digital CMOS process, this audio amplifier can operate from a single power-supply of 1.8V down to 1V, without significant change in performance. It has a measured total-harmonic-distortion (THD) at the speaker terminals of less than 0.07%, with a dynamic range (DR) of 85 dB. An efficiency of 76% can be achieved with a 4.3-/spl Omega/ speaker. The maximum output power is 350mW (rms) from a single 1.8-V power-supply, and the stand-by power consumption is only 7.5mW (load connected). This work demonstrates the feasibility of implementing class-D amplifiers with a high-end audio performance in low-voltage environments. View full abstract»

This paper presents an optimal control scheme for a multilevel inverter working for audio power amplification. The proposed control scheme comprises two loops of feedback around a sliding-mode quantizer. The double-loop feedback generates a continuous equivalent control signal, while the quantizer that operates in the sliding mode converts the equivalent control signal into a staircase voltage waveform used to drive a loudspeaker through an LC filter for audio signal tracking. The control scheme is optimized to reduce the frequency weighted tracking error and the equivalent control signal simultaneously, compromising between a satisfactory performance and a wide stable input range. With the proposed design, a nine-level class-D audio amplifier is built and tested, which exhibits high-robustness and high-quality audio reproduction. View full abstract»

The design of a fully integrated, filterless, class-D audio amplifier in standard 0.25- CMOS technology is described: a novel class-D amplifier architecture, where uniform pulsewidth modulation is introduced. The architecture attenuates residual clock signals around the loop allowing very low harmonic distortion, , to be achieved in conjunction with high PSRR, at 217 Hz. When driving 1.2 W into an 8- load, it achieves an SNR of 103 dB (A-weighted) with an efficiency of . The maximum output power at 1% THD is 3.1 W. Figures of merit are defined to establish that the amplifier exceeds the performance of alternative designs. The amplifier occupied a chip area 1.44 and was packaged as a WLCSP. View full abstract»

This paper presents the design and implementation of a high-performance fully-digital PWM DAC and switching output stage which can drive a speaker in portable devices, including cellular phones. Thanks to the quaternary pulse-width modulation scheme, filter-less implementation are possible. A pre-modulation DSP algorithm eliminates the harmonic distortion inherent to the employed modulation process, and an oversampling noise shaper reduces the modulator clock speed to facilitate the hardware implementation while keeping high-fidelity quality. Radiated electromagnetic field emission of the class D amplifier is reduced thanks to a clock spreading technique with only a minor impact on audio performance characteristics. Clock jitter effects on the audio amplifier performance are presented, showing very low degradation for jitter value up to a few nanoseconds. The digital section works with a 1.2 V power supply voltage, while the output switching stage and its driver are supplied from a high-efficiency DC-DC converter either at 3.6 V or 5 V. An output power of 0.5 W at 3.6 V and 1 W at 5 V over an 8 Ω load with efficiency (digital section included) of about 79% and 81%, respectively, has been achieved. The total harmonic distortion (THD) at maximum output level is about 0.2%, while the dynamic range is 104 dB A-weighted. The active area is about 0.94 mm² in a 0.13 μm single-poly, five-metal, N-well digital CMOS technology with double-oxide option (0.5 μm minimum length). View full abstract»

A 100 W, 5.1-channel, single-chip, digital-input class-D audio amplifier with a low-voltage (LV) digital circuit and high-voltage (HV) switching power stage is designed for moderate-performance and cost-effective speaker systems. The LV portion, including multi-channel audio processors, delta-sigma modulators (DSMs), and pulse-width modulation (PWM) generators, is implemented with a standard CMOS digital cell-library. A dual-loop resonator is proposed to increase the stable input range of the DSM so that the low-distortion output power of the class-D amplifier can be increased. For the HV portion, distortion caused by parasitic resistances of the power stage is analyzed to obtain a better design. A multi-phase PWM switching technique is proposed to prevent the multi-channel output stages from simultaneously switching, and thus the supply bouncing can be reduced. An over-current protection circuit with high supply noise immunity is also presented. Fabricated with 0.35/3-μm 3.3/18-V 1P3M CMOS technology, the 5.1-channel amplifier achieves a total root-mean-square (RMS) output power of 100 W, a distortion of less than 0.7%, and a power efficiency of 88% with a total chip area of 48.9 mm². View full abstract»

This work presents a new class-D stereo audio amplifier using three-phase full bridge circuit configuration, which is controlled by a new switching method for the current control. In the proposed switching method, the switching device of upper arm or lower arm of the bridge circuit independently acts according to the polarity of the reference current without dead time, which is inserted to prevent the arm short. Therefore, the proposed switching method is very useful for high frequency switching. Also three-phase full bridge circuit is proposed as a main circuit for the class-D stereo amplifier. The proposed circuit can reduce two switching devices compared with the conventional stereo amplifier uses two full bridge circuits. In this paper, the specified strategy for driving stereo amplifier with three-phase full bridge circuit is discussed. With the experimental results, usefulness of the proposed amplifier is confirmed. View full abstract»

The acoustic feedback causes a howling phenomenon in an audio amplifier system. This problem does not only annoy hearing but also can damage an amplifier system. The IIR adaptive howling suppressor (AHS) in an audio amplifier system is thus proposed in this paper. The algorithm of adaptive process is achieved by using the variable momentum least mean square (VMLMS). With this algorithm, the performance improvement and higher convergence rate can be success. The proposed AHS, which is placed between a preamplifier section and a power amplifier section, acts as a narrow bandwidth notch filter whose frequency characteristic can reduce a howling spectrum. The simulation results show good improvement in the howling suppression of the proposed AHS system. Moreover, the performance comparisons show that the proposed system is performed over the AHS conventional FIR and FALE structures at the same environment condition. View full abstract»

An audio amplifier was simulated, designed, built and tested, based on a switching technique, by means of a monophasic inverter. Variable width pulses control the monophasic inverter switching. The duration of each pulse was established by comparing the input (reference signal) and a sample of the amplified output signal, the difference between both produces the error signal that determines in real time the pulse width. A lowpass filter was connected to the inverter output the principal function of which was to eliminate the high frequencies due to the inverter chopping. This amplifier can work with any signal shape inside its bandwidth and also corrects the nonlinearities from the system. Distortions lower than 1% can be obtained with this kind of amplifier. This technique leads to two main advantages: high power amplifiers with high efficiency; and (2) a considerable reduction in the amplifier size View full abstract»

A new and simple configuration of filterless class D audio amplifier is proposed in this paper. The proposed filterless class D audio amplifier provides the advantages of both low total system cost and generation of synchronized 3-level pulse-width modulated (PWM) output. Moreover, as a result of hysteresis window variation, a close to constant switching frequency of PWM output is obtained. The proposed filterless class D audio amplifier is verified by the PSpice simulation and prototype circuit experiment View full abstract»

A low distortion third-order self-oscillating class D audio amplifier is integrated in a 0.7-μm CMOS process. It can deliver 1.4 W into an 8 Ω load with 5 V power supply. The presented amplifier eliminates the requirement for a high quality carrier. It achieves a dynamic range (DR) of 116.5 dB, and a peak THD+N of 0.0012% for a 1 kHz sinusoidal input. The efficiency is 84.5%. The area of the amplifier is 6 mm². View full abstract»