A real-time transmission strategy that adapts network conditions rapidly is brought forward, and it is applied to H.264 encoding standard. Firstly, the strategy forecasts initial network bandwidth using bi-search algorithm, and establishes a dropout rate-smoothing model. In addition, it adopts the AIMD algorithm to adjust the sending bit rates, and then calculates QP based on R-D model. Finally, it encodes the video sequences according to the QP that goes through the operation of smoothness. The result of experiment in model JM shows that, this method reduces the image dithering caused by the change of bit rate, makes better use of network, and improves the video quality. View full abstract»

This paper presents a simple but effective macroblock (MB) layer rate control (RC) scheme for H.264/AVC with low complexity. First, to reduce computation cost and inaccuracy of linear mean absolute difference (MAD) prediction at MB layer adopted in JVT-G012, MAD is computed directly according to the difference between current original MB and the reference blocks pointed by estimated MV using intensive motion similarity. Then, MB header bits are predicted based on spatial-temporal correlation because it is not constant due to complicated coding modes and high compression efficiency of H.264. Finally, MB target bit rate is allocated according to its complexity and the parameters of quadratic R-D model are updated using coded MBs with high spatial-temporal correlation and motion similarity not the last coded data points. Simulation results show that the proposed scheme achieves an average PSNR gain of 0.37 dB, meets better with target bit rate, produces more consistent quality for the MBs in a frame and thus improves visual quality compared to classic JVT-H017 RC algorithm, simultaneously has lower computation complexity and suits for real-time application. View full abstract»

Rateless codes can be advantageously used to provide Application Layer Forward Error Correction (AL-FEC) with a distinct advantage that an infinite number of packets can be generated on the fly from the source packets. For heterogeneous users and/or variable channel conditions, significant adaptation features and improvement in the video quality can be achieved by partitioning the video data into different priority classes. Such partitioned data can be unequally protected using appropriate FEC scheme based on its contribution to video reconstruction. Expanding Window Random Linear Codes (EW RLC) are a simple unequal error protection fountain coding scheme which can adapt to the prioritized data transmission. In this paper, EW RLC are proposed for broadcasting the H.264/Advanced video coding partitioned with the data partitioning feature. The results show viability of the EW RLC for multimedia broadcast applications to suit different data rates and channel conditions. View full abstract»

H.264 is the latest video compression standard with the highest coding efficiency, and the All-Binary Integer Motion Estimation algorithm (H.264-ABIME) is usually adopted for reducing the hardware area. There are many repeated modules in the H.264-ABIME block, thus the well-known Iterative-Logic-Array (ILA) architecture can be applied to test all the modules with constant number of test patterns. The most important condition for the ILA architecture is that the I/O function of each module should be bijective (reversible). However, most of the original designs do not have this property. In this paper, effective design-for-testability schemes are proposed by using the ILA architecture for the entire H.264-ABIME block. The repeated modules are modified to be bijective and cascaded as the ILA architecture. Then each module can be fully tested by only testing the first module exhaustively. A simple built-in self-test circuit is also proposed. Moreover, the physical designs of the scan-chain and the proposed test schemes are synthesised with the UMC 0.18 m technology. The total test time of the proposed method is only about 13.53 of that of scan-chain method with automatic test pattern generation (ATPG), and the hardware and delay-time overheads are still very low. View full abstract»

The UMHexagonS algorithm has been accepted for the possible implementation of the block motion estimation process in the H.264 video coding standard due to its high accuracy and low computational requirement. And there were also many modifications coming up with it. In article, the author offered several improvements which reduce the computational complexity of the UMHexagonS algorithm with a little loss of its accuracy. And In this paper, a new algorithm is proposed, which bases on the UMHexagonS algorithm and in two aspects. Firstly, a new prediction vector is added to replace the way of median vector. Secondly, we propose an Irregular-cross template in place of the primary unsymmetrical-cross one. The simulation results show that this two proposed methods reduce the motion estimation time by from 10% to 27% than UMHexagonS according to different types of sequences with negligible coding loss. View full abstract»

Variable block sizes, complex spatial motion vector prediction, particular skip and direct temporal MV prediction contribute to superior performance of H.264 standard. However, high irregularity of its MV prediction algorithm also makes efficient hardware implementation challenging. In this paper, an efficient VLSI architecture is proposed for irregular MV prediction implementation. Complex control logic is simplified by regularly lookuping control parameters in a predefined table. The parameters of the current MB and neighboring blocks are also initialized and updated regularly. Pipeline and parallelism are jointly employed in the proposed architecture to shorten the processing time and minimize hardware consumption. Moreover, highly regular architecture also simplifies the function verification considerably. Simulation results verify the effectiveness of the proposed design. View full abstract»

We propose a novel class of short block codes (SBCs) designed for guaranteed convergence to an infinitesimally low bit error ratio (BER), which relies on the joint optimisation of soft-bit assisted iterative source and channel decoding. An iterative detection aided combination of SBC assisted soft-bit source decoding (SBSD) and a rate-1 precoder was used to evaluate the attainable performance of the proposed scheme for transmission of data-partitioned (DP) H.264 source coded video over correlated narrowband Rayleigh fading channels. Additionally, we demonstrated the effects of different SBCs having diverse minimum Hamming distances [d_H,min] but identical coding rates on both the overall BER performance as well as on the objective video quality expressed in terms of the Peak Signal-to-Noise Ratio (PSNR). The convergence behaviour of the iterative decoding scheme using SBCs as a function of d_H,min is analysed by utilising extrinsic information transfer (EXIT) charts. Explicitly, our experimental results show that the proposed error protection scheme using SBCs associated with d_H,min = 6 outperforms the identical-code-rate SBCs having d_H,min = 3 by about 3 dB at the PSNR degradation point of 1 dB. Additionally, an E_b/N_o gain of 27 dB is attained using iterative soft-bit source and channel decoding with the aid of rate-1/3 SBCs relative to the identical-rate benchmarker. View full abstract»

In this paper, a new error concealment algorithm for the new coding standard H.264 is presented. The algorithm consists of a block size determination step to determine the size type of the lost block and a motion vector recovery step to find the lost motion vector from multiple reference frames. The main feature of this algorithm are as follows. In the block size determination step, we propose a criterion to determine the size type of the lost block from the current frame. In the motion vector recovery step, the optimal motion vector for the lost block chosen from multiple previous reference frames with the minimum value of the side match distortion. The proposed algorithm not only can determine the most correct mode for the lost block, but also can save much more computation time for motion vector recovery. Experimental results show that the proposed algorithm achieves 0.4∼7 dB improvement over the conventional VM method. View full abstract»

Exploiting thread-level parallelism is a promising way to improve the performance of multimedia applications running on multithreading general-purpose processors. This paper describes our work in developing the first multithreading implementation of the H.264 encoder. We parallelize the encoder using the OpenMP programming model, which allows us to leverage the advanced compiler technology in the Intel® C++ compiler for Intel hyper-threading architectures. We present our design considerations in the parallelization process. We describe an efficient multi-level data partitioning scheme that increases performance of a multithreaded H.264 encoder. Our experiments show parallel speedups ranging from 4.31x to 4.69x on a 4-CPU Intel Xeon™ system with hyper-threading technology. View full abstract»

This paper presents a method for transcoding from H.264 to MPEG-2. This process is divided into two parts: Intra frame transcoding and inter frame transcoding. For intra frame transcoding the brute force method of encoding and decoding in H.264 and re encoding in MPEG-2 is applied. In inter frame transcoding the motion vector information from the H.264 decoding stage is reused in the MPEG-2 encoding stage leading to significant savings in the transcoding time with very less degradation in terms of PSNR when compared to an MPEG-2 encoded decoded sequence. View full abstract»

For very low bit rate video coding, coarse-quantized DCT coefficients induce discontinuities at block boundaries, namely, blocking artifacts. Furthermore, motion-compensated prediction propagates blocking artifacts to inner-block regions of subsequent video frames. Blocking artifacts caused by motion-compensated prediction (MCP) can be solved by a loop-filter. The main drawback of loop-filter is its in-flexibility. In this study, a post deblocking filter for H.264 video is proposed. In this study, to estimate inner-block discontinuities, a motion-compensated based approach is proposed. A map of detected blocking artifacts within each video frame is stored. Combining motion vectors and blocking artifact maps of previous frames, possible locations of blocking artifacts can be estimated. Cooperating with oriented blocking artifact detection and filtering, a post deblocking filter having loop-filter performance is established. The proposed approach can also used in other DCT/MCP based codecs. View full abstract»

Based on the discrete cosine transform (DCT) coefficients distribution, an effective method of early detecting all-zero discrete cosine coefficients blocks in H.264 is proposed. A mathematic model is established based on Laplacian distribution of DCT coefficients and a criterion under which each quantized coefficient becomes zero is derived. The simulation results show that compared to the Xie's method built on Gaussian distribution, the proposed method reduces encoding time averagely without video-quality degradation for low or middle bit-rate video sequences. View full abstract»

This paper presents a method to reduce the computation and memory access for variable block size motion estimation (ME) using pixel truncation. Previous work has focused on implementing pixel truncation using a fixed-block-size (16 times 16 pixels) ME. However, pixel truncation fails to give satisfactory results for smaller block partitions. In this paper, we analyze the effect of truncating pixels for smaller block partitions and propose a method to improve the frame prediction. Our method is able to reduce the total computation and memory access compared to conventional full-search method without significantly degrading picture quality. With unique data arrangement, the proposed architectures are able to save up to 53% energy compared to the conventional full-search architecture. This makes such architectures attractive for H.264 application in future mobile devices. View full abstract»

Wireless video communication is an important application supported by 3G mobile communication systems. Motivated by the wide adoption of H.264 and the demand of universal multimedia data access over wireless network, this paper presents a fast video transcoder, working entirely in the DCT-domain, to convert high quality H.264 bitstream into low bit rate stream with low spatial resolution for wireless video access, furthermore, a motion vector estimation algorithm based on mapping and merging process is proposed to utilize the original motion information to predict motion vectors for the downscaled video. Simulation results show that, compared with the conventional transcoder, the proposed method significantly reduces the transcoding complexity while maintaining comparable rate distortion performance. View full abstract»

This paper proposes an iterative joint source-channel decoding (IJSCD) scheme for the transmission of H.264 compressed video over a noisy channel. It uses channel coding along with H.264 semantic verification. The structure, selection of design parameters, and performance of the proposed IJSCD based on a rate-% recursive systematic convolutional (RSC) code over an AWGN channel are described and discussed as an illustrative example. In the example, for the same PSNR, the proposed IJSCD scheme offers a significant saving of 2.1dB in required channel SNR as compared to a system using the same RSC code alone. Furthermore, the performance can be improved by iterative decoding at the cost of increased delay. Hence, a tradeoff can be made between performance improvement and delay View full abstract»

To reduce the size and bandwidth requirement of a frame memory for video compression, a number of memory recompression algorithms have been proposed. These previous algorithms are performed independently of a video compression standard and therefore do not take advantage of the information obtained during the processing of the compression standard. This paper proposes a new recompression algorithm that makes use of the information from H.264 intra prediction results. The proposed algorithm decomposes a frame into 4times4 blocks which are then compressed into 64-bit segments. The result of 4times4 intra prediction is used to select the scan order of the 4times4 block and DPCM (differential pulse code modulation) is performed along this scan order. Then, the DPCM results are further compressed by Golomb-Rice coding. The proposed recompression algorithm is implemented in hardware and integrated with an H.264 encoder. The proposed algorithm improves the average PSNR by 2.9dB compared to the previous work in (Lee, 2003). The hardware cost for the implementation of the recompression algorithm is 28 K gates and the additional latency to read the compressed frame memory is 162 cycles per a macroblock View full abstract»

This paper introduces an error concealment algorithm for P frame in video images that based on the error concealment algorithm in the reference software of H.264, which makes it extremely easy and flexible to obtain the best performance of error concealment at the decoder, and describes the theoretical foundation and realization in detail. External boundary matching algorithm (EBMA) based on calculate the difference of external nearby pixel between reference block and lost block which could better adapts to the characteristics of alterable blocks in motion estimation and improve the effect of error concealment of lost MB. The result of the proposed algorithm implemented on JM version 8.6 shows that have some advantages and practicality. View full abstract»

H.264 is the current state-of-the-art monoscopic video codec providing almost twice the coding efficiency with the same quality comparing the previous codecs. With the increasing interest in 3D TV, multi-view video sequences that are provided by multiple cameras capturing the three dimensional objects and/or scene are more widely used. Compressing multi-view sequences independently with H.264 (simulcast) is not efficient since the redundancy between the closer cameras is not exploited. In order to reduce these redundancies, we propose a multi-view video codec based on H.264 using disparity estimation/compensation as well as motion estimation/compensation. In order to effectively search for disparity/motion without increasing computational complexity, we modified the buffering structure of H.264 and implemented several referencing modes. Our results show that for closely located cameras, our codec outperforms simulcast H.264 coding. For sparsely located cameras, our method can still improve coding gain depending on the video characteristics View full abstract»

This paper proposes a novel implementation of the core processors, the integer transform and quantization for H.264 video encoder using an FPGA. It is capable of processing the picture frames with the desired compression controlled by the user input. The algorithm and architecture of the components of the video encoder namely, integer transformation, quantization were developed, designed and coded in Verilog. The complete H.264 video encoder was coded in Matlab in order to verify the results of the Verilog implementation. The processor is implemented on a Xilinx Vertex -II Pro XC2VP30 FPGA. The gate count of the implementation is approximately 1,057,000 working at a frequency of 208 MHz. It can process 1024×768 pixel color images in 4:2:0 format at 25 frames per second. The reconstructed picture quality is better than 35 dB. View full abstract»

In this paper, a novel weighted cross prediction (WCP) mode is proposed to replace DC mode in Intra_4times4 prediction of H.264/AVC. In the proposed scheme, the upper right part of one 4times4 block mainly employs vertical prediction while the lower left part mainly uses horizontal prediction, predicting both in vertical and horizontal directions in one block. This scheme uses simple prediction equations with fixed weighting coefficients. Experimental results show that WCP has improvement compared to H.264 and it is very competitive while comparing to other Intra_4times4 prediction algorithms. View full abstract»

During transcoding, the coefficients have to pass through another quantization step. This introduces re-quantization errors to the coefficients. H.264 integer transform and quantization features are different from those of MPEG2 and other standards. Based on these features, in MPEG2 to H.264 transcoding, an efficient algorithm that measures the re-quantization error is proposed. Then this measured error is used to compensate for the quality loss in transcoding. The experimental results from four typical video test sequences show that the proposed compensation procedure improves the PSNR value by about 4.82 dB. The error calculation and compensation could be carried in the transform domain resulting in significant computational saving View full abstract»

In this paper, we address the problem of mapping H.264 main profile decoder on embedded dual core with dynamic load balancing. H.264 decoder is mapped to dual core system with a few hardware accelerators by proposed functional partitioning which enables simple interface with hardware accelerator and small memory usage for inter-core communication. We also propose dynamic load balancing method for the functional partitioning. The load balancing is done by mapping a few selected functions to each core dynamically at macroblock level. In this case, buffer level information is enough for making decision which core runs those functions. Because of this simple decision criterion and mechanism, performance loss for load balancing process can be negligible and it is also possible to extend the proposed load balancing method to multi-core systems easily. Experimental result shows that the proposed load balancing method reduces the waiting overhead dramatically and the reduced amount is 82.3% of the total waiting overhead. View full abstract»

H.264 intra prediction algorithm has a very high computational complexity. This paper proposes a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware significantly. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are similar, the prediction equations of H.264 intra prediction modes are simplified for this block. The proposed technique reduces the amount of computations performed by 4x4 luminance, 16x16 luminance, and 8x8 chrominance prediction modes up to 68%, 39%, and 65% respectively with a small comparison overhead. The proposed technique does not change the PSNR for some video frames, it increases the PSNR slightly for some video frames and it decreases the PSNR slightly for some video frames. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. The proposed technique reduced the power consumption of this hardware up to 57%. View full abstract»