Owing to the extremely high intrinsic thermal conductivity of graphene, the thermal bottleneck in graphene devices, which are usually fabricated on Si/SiO₂ substrates, is the thermally resistive SiO₂ layer. In order to increase the breakdown current density and device reliability one can consider replacing SiO₂ with another dielectric, which has smaller thermal resistance at elevated temperatures. Here we report characteristics of the top-gate graphene field-effect transistors (G-FETs) fabricated on the ultra-nanocrystalline diamond (UNCD) layers grown by the chemical vapor deposition (CVD) on Si. We found that the graphene-on-diamond devices have increased breakdown current density by ~50% compared to the reference devices fabricated on Si/SiO₂ and to the values reported in literature. Although UNCD/Si substrates are more thermally resistive at room temperature than Si wafers, they start to outperform Si at elevated temperatures close to the thermal breakdown point. View full abstract»

We report the fabrication and characterization of double-gated Si nanowire field effect transistors with excellent current-voltage characteristics, low subthreshold slope ~85 mV/dec and high on/off current ratio ~10⁶. The Si nanowire devices are fabricated by using a self-aligned technique with standard photolithographic alignment and metal lift-off processes, enabling the large-scale integration of high-performance nanowire devices. We have also studied the effect of device structure and forming gas rapid thermal annealing on the nanowire transistor's electrical properties. We conclude that the self-aligned fabrication and non-overlapped gate-source/drain structure combined with appropriate post annealing leads to the excellent observed device performance. View full abstract»

The capacitance density of industrial low-cost metal-insulator-metal (MIM) capacitor in Cu back-end-of-line (BEOL) technologies has been improved to 1.5 fF/μm² which is 50% higher than the current foundry standard of 1.5 fF/μm² based in J. C. Guo et al. (2003), P. Zurcher et al. (2002) and C. H. Ng et al. (2002). In this paper, we present a method to fabricate the high-density MIM with only one additional mask required on lop of the standard logic baseline Cu BEOL technologies. This MIM capacitor's reliability, voltage and temperature coefficients, thermal stability, and mismatching performance have been proved to be fully qualified to meet foundry's requirements. Without applying novel material nor using extra offsetting process loop, the proposed MIM capacitor has a very good performance-over-cost ratio, which is promising to be implemented in 0.13μm and below Cu BEOL technologies. View full abstract»

We report high performance Bragg gratings in As₂S₃ chalcogenide glass rib waveguides, written with a modified Sagnac interferometer for the first time. Grating growth dynamics obtained from an in-situ monitoring system are presented and analyzed View full abstract»

This paper presents fabrication and RF characterization results of spiral inductors fabricated using a developed damascene-like thick-copper/polyimide process module. This module has low thermal budget and is compatible with current IC interconnect architectures, making it suitable for CMOS above IC integration of high quality factor passive devices. Thick, high-conductive copper layers associated with low K polymers and high resistivity substrates can provide RF performances that cannot be achieved using conventional thin aluminum films on low-resistivity substrates. Peak quality factors of about 20 and exceeding 10 over a wide frequency range (1-6 GHz) are demonstrated, with a self-resonant frequency of about 10 GHz. Measurements and equivalent circuit extraction results are also presented and discussed. View full abstract»

In this paper, the design and fabrication of a multi-material high-performance micropump is presented. Exceptional flow rates of 90 ml/min were achieved by appropriate design optimization. Manufacturing steps such as laser welding and hot embossing were successfully realized and provide a robust and scalable production technique for the micropump. Characterization of the pump demonstrated high repeatability of the air flow rate as well as long life. Analytical modeling successfully predicts the behaviour of the pump with regard to inertial effects. View full abstract»

This paper presents the design, fabrication, and characterization of temperature sensitive quartz resonators fabricated using heterogeneous integration methods for realizing high-density, thermal conductance fluctuation limited thermal sensors for infrared imaging and biochemical sensing applications. An integrated quartz sensor array using CMOS-compatible micromachining techniques has been designed and fabricated. 241 MHz micromachined resonators from Y-cut quartz crystal cuts were fabricated with a temperature sensitivity of 22.162 kHz/°C. Infrared measurements on the resonator pixel resulted in a noise equivalent power (NEP) of 3.90 nW/Hz^1/2, detectivity D* of 9.17 ×10⁷ cmHz^1/2/W, and noise equivalent temperature difference (NETD) in the 8-12 μm wavelength region of 4 mK and a response time of <;30 Hz. In a unique new application a remotely coupled thermal sensor configuration was used to monitor biochemical reactions in real time. View full abstract»

High performance logic ICs are rapidly migrating from peripheral bonded package configurations to area array, flip chip configurations. Total die I/O is exploding from <800 pins to more than 3500 pins with little abatement in the rate of increase in total silicon area. Traditional flip chip package substrate technologies, such as co-fired ceramic, are not able to adequately support this growing industry trend due to inherent limitations in thermal cycling reliability of the level 2 interface, density, electrical performance, and cost of use. A new, cost effective, organic flip chip package substrate technology has been developed, prototyped, qualified, and is being ramped into production. This laminated technology uses a nonwoven polytetrafluoroethylene (PTFE) composite dielectric combined with a fabrication technology that has produced the highest density organic substrates yet disclosed. The technology has been used to fabricate packages for die up to 18.5 mm by 18.5 mm with more than 3800 total I/O. Body sizes of up to 45 mm have been fabricated. In this paper, we will discuss the materials of construction, process technology, reliability characterization, thermo-mechanical characterization, and electrical performance of various cross-sections using this new technology View full abstract»

Axial Ge/Si heterostructure nanowires allow energy band-edge engineering along the axis of the nanowire, which is the charge transport direction, and allows the realization of novel asymmetric device architectures. This work reports on two advances in the area of heterostructure nanowires and tunnel FETs: (i) the realization of 100 % compositionally modulated Si/Ge axial heterostructure nanowires with lengths suitable for device fabrication and (ii) the design and implementation of Schottky barrier tunnel FETs on these nanowires for high-on currents and suppressed ambipolar behavior. Initial prototype devices resulted in a current drive in excess of 100 μA/μm (I/πD) and 10⁵ I_on/I_off ratios. These results demonstrate the potential of such asymmetric heterostructures (both in the semiconductor channel and at the metal-semiconductor interfaces) for low-power and high performance electronics. View full abstract»

This paper reports a novel method for producing low ohmic contact resistance, R_C, as well as low sheet resistance, R_sh, on AlN/GaN MOS-HEMT structures. The method relies on the protection of the very sensitive AlN epi-layer from exposure to liquid chemicals during processing using evaporated Al, which on thermal oxidation forms Al₂O₃. The Al₂O₃ acts as a surface passivant and as a gate dielectric for transistors that are then fabricated. In contrast to previous approaches, the ohmic contact regions are prepared for metal deposition only using wet etching with 16H₃PO₄:HNO₃:2H₂O aluminium etch solution and so no damage to the surface associated with dry etching techniques occurs. From the ohmic contact optimisations, low average values of R_C and R_sh of ~0.49 Ω.mm and ~159 Ω/□, respectively, extracted from transmission line method (TLM) characterisation. Fabricated two-finger AlN/GaN MOS-HEMTs with 3 μm gate length and 100 μm gate width showed good gate control of drain currents up to a gate bias of 3 V and achieved a maximum drain current, I_DSmax of ~1000 mA/mm. The peak extrinsic transconductance, G_max, of the device is ~230 mS/mm at V_DS = 4 V. Current gain cut-off frequency, f_T and maximum oscillation frequency, f_MAX were 2.8 and 7.9 GHz respectively. This approach provides a simple fabrication process for realising high performance AlN/GaN MOS-HEMT for high power and high frequency applications. View full abstract»

This paper presents the design, fabrication, and characterization of high-performance 0.1 /spl mu/m-channel CMOS devices with dual n/sup +p/sup +/ polysilicon gates on 35 /spl Aring/-thick gate oxide. A 22 ps/stage CMOS-inverter delay is obtained at a power supply voltage of 1.5 V. The highest unity-current-gain frequencies (f/sub T/) measured are 118 GHz for nMOSFET, and 67 GHz for pMOSFET.<> View full abstract»

This work explores the implementation of highly compact three dimensional (3D) integrable metamaterial based transmission lines on a low resistivity CMOS grade silicon substrate for microwave and millimeter wave applications. The composite right-left handed (CRLH) architecture is able to be integrated with an integrated circuit (IC) using a multilayer surface micromachined fabrication process as a post-CMOS process. The fabrication process employs the negative tone photo sensitive Benzocyclobutene (BCB) as a low-loss dielectric interlayer material allowing packaging compatible high performance RF circuits. Since the low temperature and multilayer fabrication is compatible with CMOS/MEMS processes, it allows the batch fabrication of multiple devices and the easy implementation of 3D vertical interconnects. The design, modeling, fabrication and on-wafer characterization are presented for 50 Ω compact multilayer finite ground coplanar waveguide (FGC) CRLH unit cells and transmission lines for broadband and multiband operation at Ku and Ka frequencies of 14 GHz and 35 GHz, respectively. Also, the comparison between the simulation and measurement results up to 40 GHz on the aforementioned 3D electromagnetic structures is provided. The left handed capacitance and inductance components of the CRLH structures are implemented with photolithographically defined Metal-Insulator-Metal (MIM) capacitors and BCB embedded meander inductors, respectively, which allows the fabrication of very compact CRLH devices. The fabricated dual band unit cell features a size of λ₀/30 at 14 GHz and an insertion loss of less than 2dB within the passband. View full abstract»

The continually increasing heat generation rates in high performance electronics, radar systems and data centers require development of efficient heat exchangers that can transfer large heat loads. In this paper, we present the design of a new high-performance heat exchanger capable of transferring 1000 W while consuming less than 33 W of input electrical power and having an overall thermal resistance of 0.05 K/W. The low thermal resistance is achieved by using a loop heat pipe with a single evaporator and multiple condenser plates that constitute the array of fins. Impellers between the fins are driven by a custom permanent magnet synchronous motor in a compact volume of 0.1 × 0.1 × 0.1 m to maximize the heat transfer area and reduce the required airflow rate and electrical power. The design of the heat exchanger is developed using analytical and numerical methods to determine the important parameters of each component. The results form the basis for the fabrication and experimental characterization that is currently under development. View full abstract»

A piezoelectrically driven hydraulic amplification microvalve for use in compact high-performance hydraulic pumping systems was designed, fabricated, and experimentally characterized. High-frequency, high-force actuation capabilities were enabled through the incorporation of bulk piezoelectric material elements beneath a micromachined annular tethered-piston structure. Large valve stroke at the microscale was achieved with an hydraulic amplification mechanism that amplified (40×-50×) the limited stroke of the piezoelectric material into a significantly larger motion of a micromachined valve membrane with attached valve cap. These design features enabled the valve to meet simultaneously a set of high frequency (≥1 kHz), high pressure(≥300 kPa), and large stroke (20-30 μm) requirements not previously satisfied by other hydraulic flow regulation microvalves. This paper details the design, modeling, fabrication, assembly, and experimental characterization of this valve device. Fabrication challenges are detailed. View full abstract»

This work focuses on the development and characterization of device quality thin-film crystalline silicon layers directly onto low-temperature glass. The material requirements and crystallographic quality necessary for high-performance device fabrication are studied and discussed. The processing technique investigated is aluminum-induced crystallization (AIC) of sputtered amorphous silicon on Al-coated glass substrates. Electron and ion beam microscopy are employed to study the crystallization process and the structure of the continuous polycrystalline silicon layer. The formation of this layer is accompanied by the juxtaposed layers of Al and Si films exchanging places during annealing. The grain sizes of the poly-Si material are many times larger than the film's thickness. Raman and thin-film X-ray diffraction measurements verify the good crystalline quality of the Si layers. The electrical properties are investigated by temperature dependent Hall effect measurements. They show that the electrical transport is governed by the properties within the crystallites rather than the grain boundaries. The specific advantages of AIC are: (1) its simplicity and industrial relevance, particularly for the processes of sputter deposition and thermal evaporation, (2) it requires only low-temperature processing at 500°C, (3) its short processing times, and (4) its ability to produce polycrystalline material with good crystallographic and electrical properties. These advantages make the poly-Si material formed by AIC highly interesting and suitable for subsequent device fabrication such as for poly-Si thin-film solar cells View full abstract»

The authors report on the fabrication and characterization of a high-performance 80-nm self-aligned T-gate AlInAs/GaInAs high electron mobility transistor (SAGHEMT). The 80 nm*50 mu m devices reported exhibit good pinchoff characteristics, high transconductance (g/sub m/=1150 mS/mm), low output conductance (g/sub ds/=120 mS/mm at RF), and state-of-the-art current gain cutoff frequency (f/sub T/=250 GHz). Modeling and analysis indicate that it is possible to significantly improve the performance of AlInAs/GaInAs SAGHEMTs by further reducing the gate length and/or optimizing the device structure.<> View full abstract»

This paper introduces a new paradigm for design and batch fabrication of isotropic 3-D spherical shell resonators. The approach uses pressure and surface tension driven plastic deformation (glassblowing) on a wafer scale as a mechanism for creating inherently smooth and symmetric 3-D resonant structures. The feasibility of the new approach was demonstrated by fabrication and characterization of Pyrex glass spherical shell resonators with millimeter-scale diameter and average thickness of 10 μm . Metal electrodes cofabricated along with the shell were used to actuate the two dynamically balanced four- and six-node vibratory modes. For 1-MHz glass-blown resonators, the relative frequency mismatch Δf/f between the two degenerate four-node wineglass modes was measured as 0.63% without any trimming or tuning. For the higher order six-node wineglass modes, the relative frequency mismatch was only 0.2%, demonstrating the potential for precision manufacturing. The intrinsic manufacturing symmetry enabled by the technology may inspire new classes of high-performance 3-D MEMS for communication and inertial navigation. View full abstract»

This paper demonstrates the application of property-tailorable perfluorocyclobutyl (PFCB) polymers to the fabrication of arrayed-waveguide grating (AWG) devices for use in wavelength division multiplexing (WDM) optical networks. This novel series of PFCB polymers exhibits low optical attenuation, high thermal stability, and tailorable refractive index, facilitating the design of high-performance photonic devices. The design, fabrication, and characterization of AWGs are reported in this paper. The fabricated devices show high thermal stability and low on-chip losses. Optimization of devices through the tailoring of material properties and fabrication process parameters is discussed. The successful fabrication of AWG highlights the potential of this material for other devices in photonic applications View full abstract»

Total-dose and single-event-effect radiation characterization of 0.25 micron test macro SRAMs fabricated at IBM's East Fishkill research foundry in un-hardened bulk and un-hardened partially-depleted SOI silicon, are reported. The design and fabrication process were optimized for high-performance and short access time using supply voltages of 2.5 V for the 64 K-bit and 1.8 V for the 144 K and 288 K-bit test macro SRAMs View full abstract»

This paper reports the design, fabrication and the characterization of an integrated optical filter for an FM discriminator. The filter is based on optical ring resonator structures which are fully reconfigurable using thermo-optical tuning. The desired characteristic, which is a linear slope with zero in a particular region, is demonstrated. This characteristic is needed in a high performance microwave photonics link with increased spurious free dynamic range. View full abstract»

Semiconductor (e.g. silicon, germanium) nanowires have gained interest as an attractive platform to fabricate field effect transistors devices because of their reduced short channel effects by comparison to planar devices. The realization of high performance nanowire devices however has been stymied primarily by large source (5) and drain (D) contact resistances. Here we report the fabrication and electrical characterization of the top-gated Ge-Si_xGe_1-x core-shell nanowire field-effect transistors (NWFETs) with highly doped S/D. The highly doped S/D, realized using low energy ion implantation, allows an efficient carrier injection into the NWFET channel. View full abstract»

This paper describes the design, fabrication, and characterization of 0.1-µm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2× performance gain over 2.5-V, 0.25-µm CMOS technology is achieved at a power supply voltage of 1.5 V. In addition, a 20× reduction in active power/circuit is obtained at a supply voltage of < 1 V with the same delay as the 0.25-micron CMOS. These results demonstrate the feasibility of high-performance and low-power room-temperature 0.1-µm CMOS technology. Beyond 0.1 µm, a number of fundamental device and technology issues must be examined: oxide and silicon tunneling, random dopant distribution, threshold voltage nonscaling, and interconnect delays. Several alternative device structures (in particular, low-temperature CMOS and double-gate MOSFET) for exploring the outermost limit of silicon scaling are discussed. View full abstract»

The successful realization of many high-performance microactuators, including many microvalves and micropumps, depends critically on the development of diaphragms which are capable of large displacements and free from fatigue. Thin nonplanar silicon diaphragms are promising candidates for such applications since they can be batch fabricated using techniques and materials that are compatible with the other portions of these devices. This paper reports the detailed simulation, fabrication, and characterization of such diaphragms, which are corrugated-bossed structures that unfold, accordion-like, to produce high boss deflections. Boron-doped diaphragms 1 mm on a side, 3 μm in thickness, and containing five 10-μm-deep corrugations produce boss deflections of more than 30 μm at 760 mmHg, in close agreement with simulations. The maximum deflection measured at diaphragm fracture is 38 μm under a 1050 mmHg differential pressure. The effects on load-deflection performance due to changes in diaphragm internal stress (residual stress), corrugation profile, and diaphragm thickness are also explored View full abstract»